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    Subject[PATCH v2 4/8] arm64: dts: add NXP S32G2 support
    Date
    Add an initial dtsi file for generic SoC features of NXP S32G2.

    Signed-off-by: Chester Lin <clin@suse.com>
    ---
    Changes in v2:
    - Add a SoC description.
    - Add an interrupt-affinity to the pmu node.
    - Move the psci node into the "/firmware" node.
    - Remove the redundant properties and white lines.
    - Remove the wrong interrupt specifier from the gic node.
    - Specify the range and cell-size of /soc [0 - 4 GiB].
    - Correct the reserved size of GICR to 512KiB [0x80000].

    arch/arm64/boot/dts/freescale/s32g2.dtsi | 99 ++++++++++++++++++++++++
    1 file changed, 99 insertions(+)
    create mode 100644 arch/arm64/boot/dts/freescale/s32g2.dtsi

    diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
    new file mode 100644
    index 000000000000..53b18671deec
    --- /dev/null
    +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
    @@ -0,0 +1,99 @@
    +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
    +/*
    + * NXP S32G2 SoC family
    + *
    + * Copyright (c) 2021 SUSE LLC
    + */
    +
    +#include <dt-bindings/interrupt-controller/arm-gic.h>
    +
    +/ {
    + compatible = "nxp,s32g2";
    + interrupt-parent = <&gic>;
    + #address-cells = <2>;
    + #size-cells = <2>;
    +
    + cpus {
    + #address-cells = <1>;
    + #size-cells = <0>;
    +
    + cpu0: cpu@0 {
    + device_type = "cpu";
    + compatible = "arm,cortex-a53";
    + reg = <0x0>;
    + enable-method = "psci";
    + next-level-cache = <&cluster0_l2>;
    + };
    +
    + cpu1: cpu@1 {
    + device_type = "cpu";
    + compatible = "arm,cortex-a53";
    + reg = <0x1>;
    + enable-method = "psci";
    + next-level-cache = <&cluster0_l2>;
    + };
    +
    + cpu2: cpu@100 {
    + device_type = "cpu";
    + compatible = "arm,cortex-a53";
    + reg = <0x100>;
    + enable-method = "psci";
    + next-level-cache = <&cluster1_l2>;
    + };
    +
    + cpu3: cpu@101 {
    + device_type = "cpu";
    + compatible = "arm,cortex-a53";
    + reg = <0x101>;
    + enable-method = "psci";
    + next-level-cache = <&cluster1_l2>;
    + };
    +
    + cluster0_l2: l2-cache0 {
    + compatible = "cache";
    + };
    +
    + cluster1_l2: l2-cache1 {
    + compatible = "cache";
    + };
    + };
    +
    + pmu {
    + compatible = "arm,cortex-a53-pmu";
    + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
    + };
    +
    + timer {
    + compatible = "arm,armv8-timer";
    + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
    + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
    + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
    + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
    + };
    +
    + firmware {
    + psci {
    + compatible = "arm,psci-1.0";
    + method = "smc";
    + };
    + };
    +
    + soc {
    + compatible = "simple-bus";
    + #address-cells = <1>;
    + #size-cells = <1>;
    + ranges = <0 0 0 0x80000000>;
    +
    + gic: interrupt-controller@50800000 {
    + compatible = "arm,gic-v3";
    + reg = <0x50800000 0x10000>,
    + <0x50880000 0x80000>,
    + <0x50400000 0x2000>,
    + <0x50410000 0x2000>,
    + <0x50420000 0x2000>;
    + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
    + interrupt-controller;
    + #interrupt-cells = <3>;
    + };
    + };
    +};
    --
    2.30.0
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