Messages in this thread | | | Date | Wed, 8 Sep 2021 10:09:31 +0800 | From | Leo Yan <> | Subject | Re: [RESEND PATCH 2/2] arm64: dts: rockchip: add Coresight debug range for RK3399 |
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On Tue, Sep 07, 2021 at 09:46:37AM -0700, Brian Norris wrote: > Per Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt. > > This IP block can be used for sampling the PC of any given CPU, which is > useful in certain panic scenarios where you can't get the CPU to stop > cleanly (e.g., hard lockup). > > Signed-off-by: Brian Norris <briannorris@chromium.org>
Looks good to me, FWIW:
Reviewed-by: Leo Yan <leo.yan@linaro.org>
> --- > > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 48 ++++++++++++++++++++++++ > 1 file changed, 48 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > index 3871c7fd83b0..c8c62637b600 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > @@ -433,6 +433,54 @@ usbdrd_dwc3_1: usb@fe900000 { > }; > }; > > + debug@fe430000 { > + compatible = "arm,coresight-cpu-debug", "arm,primecell"; > + reg = <0 0xfe430000 0 0x1000>; > + clocks = <&cru PCLK_COREDBG_L>; > + clock-names = "apb_pclk"; > + cpu = <&cpu_l0>; > + }; > + > + debug@fe432000 { > + compatible = "arm,coresight-cpu-debug", "arm,primecell"; > + reg = <0 0xfe432000 0 0x1000>; > + clocks = <&cru PCLK_COREDBG_L>; > + clock-names = "apb_pclk"; > + cpu = <&cpu_l1>; > + }; > + > + debug@fe434000 { > + compatible = "arm,coresight-cpu-debug", "arm,primecell"; > + reg = <0 0xfe434000 0 0x1000>; > + clocks = <&cru PCLK_COREDBG_L>; > + clock-names = "apb_pclk"; > + cpu = <&cpu_l2>; > + }; > + > + debug@fe436000 { > + compatible = "arm,coresight-cpu-debug", "arm,primecell"; > + reg = <0 0xfe436000 0 0x1000>; > + clocks = <&cru PCLK_COREDBG_L>; > + clock-names = "apb_pclk"; > + cpu = <&cpu_l3>; > + }; > + > + debug@fe610000 { > + compatible = "arm,coresight-cpu-debug", "arm,primecell"; > + reg = <0 0xfe610000 0 0x1000>; > + clocks = <&cru PCLK_COREDBG_B>; > + clock-names = "apb_pclk"; > + cpu = <&cpu_b0>; > + }; > + > + debug@fe710000 { > + compatible = "arm,coresight-cpu-debug", "arm,primecell"; > + reg = <0 0xfe710000 0 0x1000>; > + clocks = <&cru PCLK_COREDBG_B>; > + clock-names = "apb_pclk"; > + cpu = <&cpu_b1>; > + }; > + > cdn_dp: dp@fec00000 { > compatible = "rockchip,rk3399-cdn-dp"; > reg = <0x0 0xfec00000 0x0 0x100000>; > -- > 2.33.0.153.gba50c8fa24-goog >
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