lkml.org 
[lkml]   [2021]   [Sep]   [23]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    From
    Date
    SubjectRe: [PATCH] riscv: Add RISC-V svpbmt extension
    On Thu, Sep 23, 2021 at 3:18 PM Nick Kossifidis <mick@ics.forth.gr> wrote:
    >
    > Στις 2021-09-23 12:42, Nick Kossifidis έγραψε:
    > > Στις 2021-09-23 12:37, Anup Patel έγραψε:
    > >> On Thu, Sep 23, 2021 at 2:55 PM Nick Kossifidis <mick@ics.forth.gr>
    > >> wrote:
    > >>>
    > >>> Hello Guo,
    > >>>
    > >>> Στις 2021-09-23 10:27, guoren@kernel.org έγραψε:
    > >>> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml
    > >>> b/Documentation/devicetree/bindings/riscv/cpus.yaml
    > >>> index e534f6a7cfa1..1825cd8db0de 100644
    > >>> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
    > >>> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
    > >>> @@ -56,7 +56,9 @@ properties:
    > >>> enum:
    > >>> - riscv,sv32
    > >>> - riscv,sv39
    > >>> + - riscv,sv39,svpbmt
    > >>> - riscv,sv48
    > >>> + - riscv,sv48,svpbmt
    > >>> - riscv,none
    > >>>
    > >>> Isn't svpbmt orthogonal to the mmu type ? It's a functionality that
    > >>> can
    > >>> be present on either sv39/48/57 so why not have another "svpbmt"
    > >>> property directly on the cpu node ?
    > >>
    > >> Actually, "mmu-type" would be a good place because it's page based
    > >> memory attribute and paging can't exist without mmu translation mode.
    > >>
    > >> Also, "svpmbt" is indeed a CPU property so has to be feature
    > >> individual
    > >> CPU node. Hypothetically, a heterogeneous system is possible where
    > >> some CPUs have "svpmbt" and some CPUs don't have "svpmbt". For
    > >> example, a future FUxxx SoC might have a E-core and few S-cores
    > >> where S-cores have Svpmbt whereas E-core does not have Svpmbt
    > >> because it's an embedded core.
    > >>
    > >
    > > I should say cpuX node, not the root /cpu node. We can have an svpbmt
    > > property in the same way we have an mmu-type property.
    > >
    >
    > I'm also thinking of future mmu-related extensions, e.g. what about
    > svnapot ? Should we have mmu-type be riscv,sv39,svnapot and e.g.
    > riscv.sv39,svpbmt,svnapot ? It'll become messy.

    I agree, "mmu-type" can become longer in future but I was thinking
    if all MMU related features can simply be comma-separated values
    of one DT property.

    Alternately, we can have "riscv,svpmbt" bool DT property in each
    CPU node which will keep things simpler as compared to parsing
    comma-separate string in "mmu-type" DT property.

    Regards,
    Anup

    >
    > Regards,
    > Nick

    \
     
     \ /
      Last update: 2021-09-23 11:58    [W:2.464 / U:0.108 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site