Messages in this thread | | | Date | Thu, 23 Sep 2021 12:42:28 +0300 | From | Nick Kossifidis <> | Subject | Re: [PATCH] riscv: Add RISC-V svpbmt extension |
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Στις 2021-09-23 12:37, Anup Patel έγραψε: > On Thu, Sep 23, 2021 at 2:55 PM Nick Kossifidis <mick@ics.forth.gr> > wrote: >> >> Hello Guo, >> >> Στις 2021-09-23 10:27, guoren@kernel.org έγραψε: >> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml >> b/Documentation/devicetree/bindings/riscv/cpus.yaml >> index e534f6a7cfa1..1825cd8db0de 100644 >> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml >> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml >> @@ -56,7 +56,9 @@ properties: >> enum: >> - riscv,sv32 >> - riscv,sv39 >> + - riscv,sv39,svpbmt >> - riscv,sv48 >> + - riscv,sv48,svpbmt >> - riscv,none >> >> Isn't svpbmt orthogonal to the mmu type ? It's a functionality that >> can >> be present on either sv39/48/57 so why not have another "svpbmt" >> property directly on the cpu node ? > > Actually, "mmu-type" would be a good place because it's page based > memory attribute and paging can't exist without mmu translation mode. > > Also, "svpmbt" is indeed a CPU property so has to be feature individual > CPU node. Hypothetically, a heterogeneous system is possible where > some CPUs have "svpmbt" and some CPUs don't have "svpmbt". For > example, a future FUxxx SoC might have a E-core and few S-cores > where S-cores have Svpmbt whereas E-core does not have Svpmbt > because it's an embedded core. >
I should say cpuX node, not the root /cpu node. We can have an svpbmt property in the same way we have an mmu-type property.
Regards, Nick
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