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    SubjectRe: [PATCH v3 4/4] arm64: tegra: Add GPCDMA node for tegra186 and tegra194
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    On 27/08/2021 07:04, Akhil R wrote:
    > Add device tree node for GPCDMA controller on Tegra186 target
    > and Tegra194 target.
    >
    > Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com>
    > Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
    > ---
    > arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 +++
    > arch/arm64/boot/dts/nvidia/tegra186.dtsi | 46 ++++++++++++++++++++++++++
    > arch/arm64/boot/dts/nvidia/tegra194.dtsi | 46 ++++++++++++++++++++++++++
    > 3 files changed, 96 insertions(+)
    >
    > diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
    > index fcd71bf..71dd10e 100644
    > --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
    > +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
    > @@ -56,6 +56,10 @@
    > };
    > };
    >
    > + dma@2600000 {
    > + status = "okay";
    > + };
    > +
    > memory-controller@2c00000 {
    > status = "okay";
    > };
    > diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
    > index d02f6bf..9b565155 100644
    > --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
    > +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
    > @@ -73,6 +73,52 @@
    > snps,rxpbl = <8>;
    > };
    >
    > + gpcdma: dma@2600000 {
    > + compatible = "nvidia,tegra186-gpcdma";
    > + reg = <0x0 0x2600000 0x0 0x210000>;
    > + resets = <&bpmp TEGRA186_RESET_GPCDMA>;
    > + reset-names = "gpcdma";
    > + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
    > + #dma-cells = <1>;
    > + iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
    > + dma-coherent;
    > + nvidia,start-dma-channel-index = <1>;
    > + dma-channels = <31>;

    The above two properties are not defined in the binding doc and don't
    appear to be used.

    > + status = "disabled";
    > + };
    > +
    > aconnect@2900000 {
    > compatible = "nvidia,tegra186-aconnect",
    > "nvidia,tegra210-aconnect";
    > diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
    > index b7d5328..bc85c91 100644
    > --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
    > +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
    > @@ -72,6 +72,52 @@
    > snps,rxpbl = <8>;
    > };
    >
    > + gpcdma: dma@2600000 {

    Please correct indentation.

    > + compatible = "nvidia,tegra194-gpcdma";
    > + reg = <0x2600000 0x210000>;
    > + resets = <&bpmp TEGRA194_RESET_GPCDMA>;
    > + reset-names = "gpcdma";
    > + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
    > + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
    > + #dma-cells = <1>;
    > +
    > + iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
    > + dma-coherent;
    > +
    > + status = "disabled";

    You enable the GPC DMA for Tegra186 but not for Tegra194. Any reason why?

    Jon

    --
    nvpublic

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