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    Subject[PATCH 5.13 021/380] clk: socfpga: agilex: fix up s2f_user0_clk representation
    Date
    From: Dinh Nguyen <dinguyen@kernel.org>

    commit f817c132db679d492d96c60993fa2f2c67ab18d0 upstream.

    Correct the s2f_user0_mux clock representation.

    Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform")
    Cc: stable@vger.kernel.org
    Signed-off-by: Kris Chaplin <kris.chaplin@intel.com>
    Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
    Link: https://lore.kernel.org/r/20210713144621.605140-2-dinguyen@kernel.org
    Signed-off-by: Stephen Boyd <sboyd@kernel.org>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/clk/socfpga/clk-agilex.c | 9 +++++++++
    1 file changed, 9 insertions(+)

    --- a/drivers/clk/socfpga/clk-agilex.c
    +++ b/drivers/clk/socfpga/clk-agilex.c
    @@ -195,6 +195,13 @@ static const struct clk_parent_data sdmm
    .name = "boot_clk", },
    };

    +static const struct clk_parent_data s2f_user0_mux[] = {
    + { .fw_name = "s2f_user0_free_clk",
    + .name = "s2f_user0_free_clk", },
    + { .fw_name = "boot_clk",
    + .name = "boot_clk", },
    +};
    +
    static const struct clk_parent_data s2f_user1_mux[] = {
    { .fw_name = "s2f_user1_free_clk",
    .name = "s2f_user1_free_clk", },
    @@ -319,6 +326,8 @@ static const struct stratix10_gate_clock
    4, 0x98, 0, 16, 0x88, 3, 0},
    { AGILEX_SDMMC_CLK, "sdmmc_clk", NULL, sdmmc_mux, ARRAY_SIZE(sdmmc_mux), 0, 0x7C,
    5, 0, 0, 0, 0x88, 4, 4},
    + { AGILEX_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_user0_mux, ARRAY_SIZE(s2f_user0_mux), 0, 0x24,
    + 6, 0, 0, 0, 0x30, 2, 0},
    { AGILEX_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux, ARRAY_SIZE(s2f_user1_mux), 0, 0x7C,
    6, 0, 0, 0, 0x88, 5, 0},
    { AGILEX_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux, ARRAY_SIZE(psi_mux), 0, 0x7C,

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