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SubjectRe: [RFC PATCH V4 2/6] riscv: errata: pgtable: Add custom Svpbmt supported for Allwinner D1
On Wed, Sep 15, 2021 at 3:47 PM Christoph Hellwig <hch@lst.de> wrote:
>
> This is the wrong way around. We need to design around the PBMT
> definitions.
I've defined them in arch/riscv/include/asm/pgtable-bits.h first, that
follow current latest draft. Then I undefine them in
errata/thead/errata.c to illustrate we should follow standard PBMT,
not a custom one.

> If we want to hack in support for completely broken SOCs
> that intentionally violate the specification it should be done after
> the fact,
When c9xx was released in 2018, there is no clear direction for how to
solve the non-coherent problem. We just thought PBMT is the correct
direction, but we can't predict how encoding exactly in the highest
bits. (Maybe we should keep the highest bits zero for _P/SXXX in
pgtable.h, but it was really hard to guess at that time.) So don't
imply we "intentionally" here! When the svpbmt is frozen in the
future, we would follow that in our next-generation processor.

> in a separate patch, using alternatives and clearly documenting
> how broken these SOCs are.
Okay, I would separate errata into another patch.

About documenting, I've illustrated c9xx PTE format's detail and using
undef _PAGE_XXX to show that we replaced standard's in errata:

+/*
+ * T-HEAD C9xx PTE format:
+ * | 63 | 62 | 61 | 60 | 59-8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
+ * SO C B SH RSW D A G U X W R V
+ * ^ ^ ^ ^ ^
+ * BIT(63): SO - Strong Order
+ * BIT(62): C - Cacheable
+ * BIT(61): B - Bufferable
+ * BIT(60): SH - Shareable
+ *
+ * MT_MASK : [63 - 59]
+ * MT_PMA : C + SH
+ * MT_NC : (none)
+ * MT_IO : SO
+ */
+#undef _PAGE_MT_MASK
+#undef _PAGE_MT_PMA
+#undef _PAGE_MT_NC
+#undef _PAGE_MT_IO
+
+#define _PAGE_MT_MASK 0xf800000000000000
+#define _PAGE_MT_PMA 0x5000000000000000
+#define _PAGE_MT_NC 0x0
+#define _PAGE_MT_IO 0x8000000000000000
+#endif


--
Best Regards
Guo Ren

ML: https://lore.kernel.org/linux-csky/

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