Messages in this thread Patch in this message | | | From | Smita Koralahalli <> | Subject | [PATCH 4/5] x86/mce/inject: Check for writes ignored in status registers | Date | Wed, 15 Sep 2021 18:27:38 -0500 |
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According to Section 2.1.16.3 under HWCR[McStatusWrEn] in "PPR for AMD Family 19h, Model 01h, Revision B1 Processors - 55898 Rev 0.35 - Feb 5, 2021", the status register may sometimes enforce write ignored behavior independent of the value of HWCR[McStatusWrEn] depending on the platform settings.
Hence, evaluate for writes ignored for MCA_STATUS and MCA_DESTAT separately, before doing error simulation. If true, return with an error code.
Deferred errors on an SMCA platform use different MSR for MCA_DESTAT. Hence, evaluate MCA_DESTAT instead of MCA_STATUS on deferred errors, and do not modify the existing value in MCA_STATUS by writing and reading from it.
Rearrange the calls and write to registers MCx_{ADDR, MISC, SYND} and MCG_STATUS only if error simulation is available.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> --- arch/x86/kernel/cpu/mce/inject.c | 39 ++++++++++++++++++++++++-------- 1 file changed, 30 insertions(+), 9 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c index 8af4c9845f96..c7d1564f244b 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -457,24 +457,39 @@ static void toggle_nb_mca_mst_cpu(u16 nid) __func__, PCI_FUNC(F3->devfn), NBCFG); } +struct mce_err_handler { + struct mce *mce; + int err; +}; + +static struct mce_err_handler mce_err; + static void prepare_msrs(void *info) { - struct mce m = *(struct mce *)info; + struct mce_err_handler *i_mce_err = ((struct mce_err_handler *)info); + struct mce m = *i_mce_err->mce; u8 b = m.bank; - wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); + u32 status_reg = msr_ops.status(b); + u32 addr_reg = msr_ops.addr(b); if (boot_cpu_has(X86_FEATURE_SMCA) && m.inject_flags == DFR_INT_INJ) { - wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); - wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); - goto out; + status_reg = MSR_AMD64_SMCA_MCx_DESTAT(b); + addr_reg = MSR_AMD64_SMCA_MCx_DEADDR(b); } - wrmsrl(msr_ops.status(b), m.status); - wrmsrl(msr_ops.addr(b), m.addr); + wrmsrl(status_reg, m.status); + rdmsrl(status_reg, m.status); + + if (!m.status) { + pr_info("Error simulation is not available\n"); + i_mce_err->err = -EINVAL; + return; + } -out: + wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); + wrmsrl(addr_reg, m.addr); wrmsrl(msr_ops.misc(b), m.misc); if (boot_cpu_has(X86_FEATURE_SMCA)) @@ -487,6 +502,9 @@ static void do_inject(void) unsigned int cpu = i_mce.extcpu; u8 b = i_mce.bank; + mce_err.mce = &i_mce; + mce_err.err = 0; + i_mce.tsc = rdtsc_ordered(); i_mce.status |= MCI_STATUS_VAL; @@ -538,10 +556,13 @@ static void do_inject(void) i_mce.mcgstatus = mcg_status; i_mce.inject_flags = inj_type; - smp_call_function_single(cpu, prepare_msrs, &i_mce, 0); + smp_call_function_single(cpu, prepare_msrs, &mce_err, 0); toggle_hw_mce_inject(cpu, false); + if (mce_err.err) + goto err; + switch (inj_type) { case DFR_INT_INJ: smp_call_function_single(cpu, trigger_dfr_int, NULL, 0); -- 2.17.1
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