[lkml]   [2021]   [Sep]   [15]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
Subject[PATCH 0/5] x86/mce: Handle error simulation failures in mce-inject module
This series of patches handles the scenarios where error simulation
fails silently on mce-inject module. It also cleans up the code by
replacing MCx_{STATUS, ADDR, MISC} macros with msr_ops and finally returns
error code to userspace on failures injecting the module.

Error simulation fails if the bank is unpopulated (MCA_IPID register reads
zero) or if the platform enforces write ignored behavior on status

The first patch checks for an unpopulated bank by reading the value out
from MCA_IPID register and the fourth patch checks for writes ignored from

The second patch sets valid bit before doing error injection.

The third patch does some cleanup by replacing MCx_{STATUS, ADDR, MISC}
macros with msr_ops.

The final patch returns error code to userspace from mce-inject module.

Smita Koralahalli (5):
x86/mce/inject: Check if a bank is unpopulated before error simulation
x86/mce/inject: Set the valid bit in MCA_STATUS before error injection
x86/mce: Use msr_ops in prepare_msrs()
x86/mce/inject: Check for writes ignored in status registers
x86/mce/mce-inject: Return error code to userspace from mce-inject

arch/x86/kernel/cpu/mce/core.c | 1 +
arch/x86/kernel/cpu/mce/inject.c | 80 ++++++++++++++++++++++++--------
2 files changed, 62 insertions(+), 19 deletions(-)


 \ /
  Last update: 2021-09-16 01:29    [W:0.163 / U:18.392 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site