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SubjectRe: [RFC PATCH v8 15/21] riscv: Add vector extension XOR implementation
On Thu, Sep 9, 2021 at 1:49 AM Greentime Hu <greentime.hu@sifive.com> wrote:
>
> This patch adds support for vector optimized XOR it is tested in spike and
> qemu.
>
> Logs in spike:
> [ 0.008365] xor: measuring software checksum speed
> [ 0.048885] 8regs : 1719.000 MB/sec
> [ 0.089080] 32regs : 1717.000 MB/sec
> [ 0.129275] rvv : 7043.000 MB/sec
> [ 0.129525] xor: using function: rvv (7043.000 MB/sec)
>
> Logs in qemu:
> [ 0.098943] xor: measuring software checksum speed
> [ 0.139391] 8regs : 2911.000 MB/sec
> [ 0.181079] 32regs : 2813.000 MB/sec
> [ 0.224260] rvv : 45.000 MB/sec
> [ 0.225586] xor: using function: 8regs (2911.000 MB/sec)
>
> Co-developed-by: Han-Kuan Chen <hankuan.chen@sifive.com>
> Signed-off-by: Han-Kuan Chen <hankuan.chen@sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> ---
> arch/riscv/include/asm/xor.h | 74 ++++++++++++++++++++++++++++++++
> arch/riscv/lib/Makefile | 1 +
> arch/riscv/lib/xor.S | 81 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 156 insertions(+)
> create mode 100644 arch/riscv/include/asm/xor.h
> create mode 100644 arch/riscv/lib/xor.S
>
> diff --git a/arch/riscv/include/asm/xor.h b/arch/riscv/include/asm/xor.h
> new file mode 100644
> index 000000000000..60ee0224913d
> --- /dev/null
> +++ b/arch/riscv/include/asm/xor.h
> @@ -0,0 +1,74 @@


[...]

>
> +extern bool has_vector;
> +#undef XOR_TRY_TEMPLATES
> +#define XOR_TRY_TEMPLATES \
> + do { \
> + xor_speed(&xor_block_8regs); \
> + xor_speed(&xor_block_32regs); \
> + if (has_vector) { \
> + xor_speed(&xor_block_rvv);\
> + } \
> + } while (0)
> +#endif
>
bool has_vector is changed to has_vector() function now, should this
change as well?


Regards
Ley Foon

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