Messages in this thread | | | From | Chen Huang <> | Subject | [PATCH 0/2] riscv: improve unaligned memory accesses | Date | Mon, 13 Sep 2021 12:19:54 +0000 |
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The RISCV ISA can support unaligned memory accesses, so the patchset selects HAVE_EFFICIENT_UNALIGNED_ACCESS and supports DCACHE_WORD_ACCESS to improve the efficiency of unaligned memory accesses.
Chen Huang (2): riscv: Kconfig: select HAVE_EFFICIENT_UNALIGNED_ACCESS riscv: Support DCACHE_WORD_ACCESS
arch/riscv/Kconfig | 2 ++ arch/riscv/include/asm/word-at-a-time.h | 36 +++++++++++++++++++++++++ 2 files changed, 38 insertions(+)
-- 2.18.0.huawei.25
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