Messages in this thread | | | Date | Tue, 3 Aug 2021 12:53:37 +0300 | From | Vladimir Oltean <> | Subject | Re: [PATCH net 1/1] net: dsa: qca: ar9331: reorder MDIO write sequence |
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On Tue, Aug 03, 2021 at 08:37:46AM +0200, Oleksij Rempel wrote: > In case of this switch we work with 32bit registers on top of 16bit > bus. Some registers (for example access to forwarding database) have > trigger bit on the first 16bit half of request and the result + > configuration of request in the second half. Without this patch, we would > trigger database operation and overwrite result in one run. > > To make it work properly, we should do the second part of transfer > before the first one is done. > > So far, this rule seems to work for all registers on this switch. > > Fixes: ec6698c272de ("net: dsa: add support for Atheros AR9331 built-in switch") > Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> > Reviewed-by: Andrew Lunn <andrew@lunn.ch> > ---
I don't really like to chase a patch to make sure my review tags get propagated, but anyway:
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
https://patchwork.kernel.org/project/netdevbpf/patch/20210802131037.32326-2-o.rempel@pengutronix.de/
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