Messages in this thread | | | Subject | Re: [RFC PATCH v2 05/69] KVM: TDX: Add architectural definitions for structures and values | From | Xiaoyao Li <> | Date | Mon, 2 Aug 2021 21:25:44 +0800 |
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On 7/31/2021 9:04 AM, Erdem Aktas wrote: > On Fri, Jul 2, 2021 at 3:05 PM <isaku.yamahata@intel.com> wrote: >> +/* Management class fields */ >> +enum tdx_guest_management { >> + TD_VCPU_PEND_NMI = 11, >> +}; >> + >> +/* @field is any of enum tdx_guest_management */ >> +#define TDVPS_MANAGEMENT(field) BUILD_TDX_FIELD(32, (field)) > > I am a little confused with this. According to the spec, PEND_NMI has > a field code of 0x200000000000000B > I can understand that 0x20 is the class code and the PEND_NMI field code is 0xB. > On the other hand, for the LAST_EXIT_TSC the field code is 0xA00000000000000A.
> Based on your code and the table in the spec, I can see that there is > an additional mask (1ULL<<63) for readonly fields
No. bit 63 is not for readonly fields, but for non_arch fields.
Please see 18.7.1 General definition
> Is this information correct and is this included in the spec? I tried > to find it but somehow I do not see it clearly defined. > >> +#define TDX1_NR_TDCX_PAGES 4 >> +#define TDX1_NR_TDVPX_PAGES 5 >> + >> +#define TDX1_MAX_NR_CPUID_CONFIGS 6 > Why is this just 6? I am looking at the CPUID table in the spec and > there are already more than 6 CPUID leaves there.
This is the number of CPUID config reported by TDH.SYS.INFO. Current KVM only reports 6 leaves.
>> +#define TDX1_MAX_NR_CMRS 32 >> +#define TDX1_MAX_NR_TDMRS 64 >> +#define TDX1_MAX_NR_RSVD_AREAS 16 >> +#define TDX1_PAMT_ENTRY_SIZE 16 >> +#define TDX1_EXTENDMR_CHUNKSIZE 256 > > I believe all of the defined variables above need to be enumerated > with TDH.SYS.INFO.
No. Only TDX1_MAX_NR_TDMRS, TDX1_MAX_NR_RSVD_AREAS and TDX1_PAMT_ENTRY_SIZE can be enumerated from TDH.SYS.INFO.
- TDX1_MAX_NR_CMRS is described in 18.6.3 CMR_INFO, which tells
TDH.SYS.INFO leaf function returns a MAX_CMRS(32) entry array of CMR_INFO entries.
- TDX1_EXTENDMR_CHUNKSIZE is describe in 20.2.23 TDH.MR.EXTEND
>> +#define TDX_TDMR_ADDR_ALIGNMENT 512 > Is TDX_TDMR_ADDR_ALIGNMENT used anywhere or is it just for completeness?
It's the leftover during rebase. We will clean it up.
>> +#define TDX_TDMR_INFO_ALIGNMENT 512 > Why do we have alignment of 512, I am assuming to make it cache line > size aligned for efficiency?
It should be leftover too.
SEAMCALL TDH.SYS.INFO requires each cmr info in CMR_INFO_ARRAY to be 512B aligned
> >> +#define TDX_TDSYSINFO_STRUCT_ALIGNEMNT 1024 > > typo: ALIGNEMNT -> ALIGNMENT > > -Erdem >
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