Messages in this thread | | | Subject | Re: [PATCH v1] drm/msm/dpu: Fix address of SM8150 PINGPONG5 IRQ register | From | Dmitry Baryshkov <> | Date | Thu, 19 Aug 2021 19:20:28 +0300 |
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On 19/08/2021 16:36, Robert Foss wrote: > Both PINGPONG4 and PINGPONG5 IRQ registers are using the > same address, which is incorrect. PINGPONG4 should use the > register offset 30, and PINGPONG5 should use the register > offset 31 according to the downstream driver. > > Fixes: 667e9985ee24 ("drm/msm/dpu: replace IRQ lookup with the data in hw catalog") > Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 2e482cdd7b3c5..420d78cfce8af 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -794,7 +794,7 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = { > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), > -1), > PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk, > - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), > -1), > }; > >
-- With best wishes Dmitry
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