lkml.org 
[lkml]   [2021]   [Jul]   [5]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
SubjectRE: [RFC v2 3/4] crypto: hisilicon/qm - Export mailbox functions for common use
Date


> -----Original Message-----
> From: Max Gurtovoy [mailto:mgurtovoy@nvidia.com]
> Sent: 04 July 2021 10:34
> To: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>;
> kvm@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux-crypto@vger.kernel.org
> Cc: alex.williamson@redhat.com; jgg@nvidia.com; Linuxarm
> <linuxarm@huawei.com>; liulongfang <liulongfang@huawei.com>; Zengtao (B)
> <prime.zeng@hisilicon.com>; yuzenghui <yuzenghui@huawei.com>; Jonathan
> Cameron <jonathan.cameron@huawei.com>; Wangzhou (B)
> <wangzhou1@hisilicon.com>
> Subject: Re: [RFC v2 3/4] crypto: hisilicon/qm - Export mailbox functions for
> common use
>
>
> On 7/2/2021 12:58 PM, Shameer Kolothum wrote:
> > From: Longfang Liu <liulongfang@huawei.com>
> >
> > Export QM mailbox functions so that they can be used from HiSilicon
> > ACC vfio live migration driver in follow-up patch.
> >
> > Signed-off-by: Longfang Liu <liulongfang@huawei.com>
> > Signed-off-by: Shameer Kolothum
> <shameerali.kolothum.thodi@huawei.com>
> > ---
> > drivers/crypto/hisilicon/qm.c | 8 +++++---
> > drivers/crypto/hisilicon/qm.h | 4 ++++
> > 2 files changed, 9 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/crypto/hisilicon/qm.c
> > b/drivers/crypto/hisilicon/qm.c index ce439a0c66c9..87fc0199705e
> > 100644
> > --- a/drivers/crypto/hisilicon/qm.c
> > +++ b/drivers/crypto/hisilicon/qm.c
> > @@ -492,7 +492,7 @@ static bool qm_qp_avail_state(struct hisi_qm *qm,
> struct hisi_qp *qp,
> > }
> >
> > /* return 0 mailbox ready, -ETIMEDOUT hardware timeout */ -static
> > int qm_wait_mb_ready(struct hisi_qm *qm)
> > +int qm_wait_mb_ready(struct hisi_qm *qm)
> > {
> > u32 val;
> >
> > @@ -500,6 +500,7 @@ static int qm_wait_mb_ready(struct hisi_qm *qm)
> > val, !((val >> QM_MB_BUSY_SHIFT) &
> > 0x1), POLL_PERIOD, POLL_TIMEOUT);
> > }
> > +EXPORT_SYMBOL_GPL(qm_wait_mb_ready);
> >
> > /* 128 bit should be written to hardware at one time to trigger a mailbox
> */
> > static void qm_mb_write(struct hisi_qm *qm, const void *src) @@
> > -523,8 +524,8 @@ static void qm_mb_write(struct hisi_qm *qm, const void
> *src)
> > : "memory");
> > }
> >
> > -static int qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16
> queue,
> > - bool op)
> > +int qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
> > + bool op)
> > {
> > struct qm_mailbox mailbox;
> > int ret = 0;
> > @@ -563,6 +564,7 @@ static int qm_mb(struct hisi_qm *qm, u8 cmd,
> dma_addr_t dma_addr, u16 queue,
> > atomic64_inc(&qm->debug.dfx.mb_err_cnt);
> > return ret;
> > }
> > +EXPORT_SYMBOL_GPL(qm_mb);
> >
> > static void qm_db_v1(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8
> priority)
> > {
> > diff --git a/drivers/crypto/hisilicon/qm.h
> > b/drivers/crypto/hisilicon/qm.h index acefdf8b3a50..18b010d5452d
> > 100644
> > --- a/drivers/crypto/hisilicon/qm.h
> > +++ b/drivers/crypto/hisilicon/qm.h
> > @@ -396,6 +396,10 @@ pci_ers_result_t hisi_qm_dev_slot_reset(struct
> pci_dev *pdev);
> > void hisi_qm_reset_prepare(struct pci_dev *pdev);
> > void hisi_qm_reset_done(struct pci_dev *pdev);
> >
> > +int qm_wait_mb_ready(struct hisi_qm *qm); int qm_mb(struct hisi_qm
> > +*qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
> > + bool op);
> > +
>
> maybe you can put it under include/linux/.. ?

Ok. I suppose we could do that.

Thanks,
Shameer

>
>
> > struct hisi_acc_sgl_pool;
> > struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device
> *dev,
> > struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool,
\
 
 \ /
  Last update: 2021-07-05 12:25    [W:2.130 / U:0.000 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site