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Subject[tip: perf/core] perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support
The following commit has been merged into the perf/core branch of tip:

Commit-ID: 2a8e51eae7c83c29795622cfc794cf83436cc05d
Gitweb: https://git.kernel.org/tip/2a8e51eae7c83c29795622cfc794cf83436cc05d
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Wed, 30 Jun 2021 14:08:34 -07:00
Committer: Peter Zijlstra <peterz@infradead.org>
CommitterDate: Fri, 02 Jul 2021 15:58:40 +02:00

perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support

M3 Intel UPI is the interface between the mesh and the Intel UPI link
layer. It is responsible for translating between the mesh protocol
packets and the flits that are used for transmitting data across the
Intel UPI interface.

The layout of the control registers for a M3UPI uncore unit is similar
to a UPI uncore unit.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-11-git-send-email-kan.liang@linux.intel.com
---
arch/x86/events/intel/uncore_snbep.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index 20045ba..14b9b23 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -5703,6 +5703,11 @@ static struct intel_uncore_type spr_uncore_upi = {
.name = "upi",
};

+static struct intel_uncore_type spr_uncore_m3upi = {
+ SPR_UNCORE_PCI_COMMON_FORMAT(),
+ .name = "m3upi",
+};
+
#define UNCORE_SPR_NUM_UNCORE_TYPES 12

static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
@@ -5715,7 +5720,7 @@ static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
&spr_uncore_imc,
&spr_uncore_m2m,
&spr_uncore_upi,
- NULL,
+ &spr_uncore_m3upi,
NULL,
NULL,
};
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