Messages in this thread | | | From | Linus Walleij <> | Date | Fri, 30 Jul 2021 11:15:01 +0200 | Subject | Re: [PATCH v3 1/2] dt-bindings: pinctrl: Add bindings for Intel Keembay pinctrl driver |
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On Fri, Jul 16, 2021 at 6:27 PM <lakshmi.sowjanya.d@intel.com> wrote:
> From: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> > > Add Device Tree bindings documentation for Intel Keem Bay > SoC's pin controller. > Add entry for INTEL Keem Bay pinctrl driver in MAINTAINERS file > > Acked-by: Mark Gross <mgross@linux.intel.com> > Co-developed-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com> > Signed-off-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com> > Co-developed-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> > Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> > Signed-off-by: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> (...) > + interrupts: > + description: > + Specifies the interrupt lines to be used by the controller. > + maxItems: 8
Write here that each interrupt is shared by up to 4 GPIO lines.
With that: Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours, Linus Walleij
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