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SubjectRe: [PATCH 1/2] mtd: spi-nor: micron-st: sync flags of mt25ql02g and mt25qu02g with other mt25q
Am 2021-07-23 13:27, schrieb Matthias Schiffer:
> All mt25q variants have the same features.
>
> Unlike the smaller variants, no n25q with 2G exists, so we don't need
> to
> match on the extended ID to distinguish n25q and mt25q series for these
> models.

But why shouldn't we? What if there will be another flash with
the same first three id bytes?

> Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
> ---
> drivers/mtd/spi-nor/micron-st.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/micron-st.c
> b/drivers/mtd/spi-nor/micron-st.c
> index c224e59820a1..d5baa8762c8d 100644
> --- a/drivers/mtd/spi-nor/micron-st.c
> +++ b/drivers/mtd/spi-nor/micron-st.c
> @@ -181,11 +181,11 @@ static const struct flash_info st_parts[] = {
> SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
> NO_CHIP_ERASE) },
> { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096,
> - SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
> - NO_CHIP_ERASE) },

This bothers me. I'm not sure how this will work. I see that
chip erase is command 0xc7, but both the new and the old flash
just supports 0xc3 (DIE ERASE). Did you test these changes?

> + SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
> + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096,
> SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
> - SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
>
> { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
> { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },

-michael

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