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    Subject[v14 21/21] clk: mediatek: Add MT8192 vencsys clock support
    Date
    Add MT8192 vencsys clock provider

    Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
    Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
    ---
    drivers/clk/mediatek/Kconfig | 6 +++
    drivers/clk/mediatek/Makefile | 1 +
    drivers/clk/mediatek/clk-mt8192-venc.c | 53 ++++++++++++++++++++++++++
    3 files changed, 60 insertions(+)
    create mode 100644 drivers/clk/mediatek/clk-mt8192-venc.c

    diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
    index 31779f2c5c83..576babd86f98 100644
    --- a/drivers/clk/mediatek/Kconfig
    +++ b/drivers/clk/mediatek/Kconfig
    @@ -574,6 +574,12 @@ config COMMON_CLK_MT8192_VDECSYS
    help
    This driver supports MediaTek MT8192 vdecsys and vdecsys_soc clocks.

    +config COMMON_CLK_MT8192_VENCSYS
    + bool "Clock driver for MediaTek MT8192 vencsys"
    + depends on COMMON_CLK_MT8192
    + help
    + This driver supports MediaTek MT8192 vencsys clocks.
    +
    config COMMON_CLK_MT8516
    bool "Clock driver for MediaTek MT8516"
    depends on ARCH_MEDIATEK || COMPILE_TEST
    diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
    index 887dd6bcf7f2..15bc045f0b71 100644
    --- a/drivers/clk/mediatek/Makefile
    +++ b/drivers/clk/mediatek/Makefile
    @@ -79,5 +79,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_MMSYS) += clk-mt8192-mm.o
    obj-$(CONFIG_COMMON_CLK_MT8192_MSDC) += clk-mt8192-msdc.o
    obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o
    obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o
    +obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o
    obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
    obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
    diff --git a/drivers/clk/mediatek/clk-mt8192-venc.c b/drivers/clk/mediatek/clk-mt8192-venc.c
    new file mode 100644
    index 000000000000..c0d867bff09e
    --- /dev/null
    +++ b/drivers/clk/mediatek/clk-mt8192-venc.c
    @@ -0,0 +1,53 @@
    +// SPDX-License-Identifier: GPL-2.0-only
    +//
    +// Copyright (c) 2021 MediaTek Inc.
    +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
    +
    +#include <linux/clk-provider.h>
    +#include <linux/of_device.h>
    +#include <linux/platform_device.h>
    +
    +#include "clk-mtk.h"
    +#include "clk-gate.h"
    +
    +#include <dt-bindings/clock/mt8192-clk.h>
    +
    +static const struct mtk_gate_regs venc_cg_regs = {
    + .set_ofs = 0x4,
    + .clr_ofs = 0x8,
    + .sta_ofs = 0x0,
    +};
    +
    +#define GATE_VENC(_id, _name, _parent, _shift) \
    + GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
    +
    +static const struct mtk_gate venc_clks[] = {
    + GATE_VENC(CLK_VENC_SET0_LARB, "venc_set0_larb", "venc_sel", 0),
    + GATE_VENC(CLK_VENC_SET1_VENC, "venc_set1_venc", "venc_sel", 4),
    + GATE_VENC(CLK_VENC_SET2_JPGENC, "venc_set2_jpgenc", "venc_sel", 8),
    + GATE_VENC(CLK_VENC_SET5_GALS, "venc_set5_gals", "venc_sel", 28),
    +};
    +
    +static const struct mtk_clk_desc venc_desc = {
    + .clks = venc_clks,
    + .num_clks = ARRAY_SIZE(venc_clks),
    +};
    +
    +static const struct of_device_id of_match_clk_mt8192_venc[] = {
    + {
    + .compatible = "mediatek,mt8192-vencsys",
    + .data = &venc_desc,
    + }, {
    + /* sentinel */
    + }
    +};
    +
    +static struct platform_driver clk_mt8192_venc_drv = {
    + .probe = mtk_clk_simple_probe,
    + .driver = {
    + .name = "clk-mt8192-venc",
    + .of_match_table = of_match_clk_mt8192_venc,
    + },
    +};
    +
    +builtin_platform_driver(clk_mt8192_venc_drv);
    --
    2.18.0
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