Messages in this thread Patch in this message | | | From | Alexandre Ghiti <> | Subject | [PATCH -fixes 2/3] Revert "riscv: Remove CONFIG_PHYS_RAM_BASE_FIXED" | Date | Wed, 21 Jul 2021 09:59:36 +0200 |
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This reverts commit 9b79878ced8f7ab85c57623f8b1f6882e484a316.
The removal of this config exposes CONFIG_PHYS_RAM_BASE for all kernel types: this value being implementation-specific, this breaks the genericity of the RISC-V kernel so revert it.
Signed-off-by: Alexandre Ghiti <alex@ghiti.fr> --- arch/riscv/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 8fcceb8eda07..6a02caf49cde 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -494,8 +494,13 @@ config STACKPROTECTOR_PER_TASK def_bool y depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_TLS +config PHYS_RAM_BASE_FIXED + bool "Explicitly specified physical RAM address" + default n + config PHYS_RAM_BASE hex "Platform Physical RAM address" + depends on PHYS_RAM_BASE_FIXED default "0x80000000" help This is the physical address of RAM in the system. It has to be @@ -508,6 +513,7 @@ config XIP_KERNEL # This prevents XIP from being enabled by all{yes,mod}config, which # fail to build since XIP doesn't support large kernels. depends on !COMPILE_TEST + select PHYS_RAM_BASE_FIXED help Execute-In-Place allows the kernel to run from non-volatile storage directly addressable by the CPU, such as NOR flash. This saves RAM -- 2.30.2
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