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    Subject[RFC PATCH v2 32/69] KVM: x86: Allow host-initiated WRMSR to set X2APIC regardless of CPUID
    Date
    From: Sean Christopherson <sean.j.christopherson@intel.com>

    Let userspace, or in the case of TDX, KVM itself, enable X2APIC even if
    X2APIC is not reported as supported in the guest's CPU model. KVM
    generally does not force specific ordering between ioctls(), e.g. this
    forces userspace to configure CPUID before MSRs. And for TDX, vCPUs
    will always run with X2APIC enabled, e.g. KVM will want/need to enable
    X2APIC from time zero.

    Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
    Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
    ---
    arch/x86/kvm/x86.c | 7 +++++--
    1 file changed, 5 insertions(+), 2 deletions(-)

    diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
    index 3407870b6f44..c231a88d5946 100644
    --- a/arch/x86/kvm/x86.c
    +++ b/arch/x86/kvm/x86.c
    @@ -437,8 +437,11 @@ int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
    {
    enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
    enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
    - u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff |
    - (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
    + u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff;
    +
    + if (!msr_info->host_initiated &&
    + !guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
    + reserved_bits |= X2APIC_ENABLE;

    if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
    return 1;
    --
    2.25.1
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