Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Fri, 16 Jul 2021 10:09:40 +0200 | Subject | Re: [PATCH 4/6] clk: renesas: r9a07g044-cpg: Add entry for fixed clock P0_DIV2 |
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Hi Prabhakar,
On Thu, Jul 15, 2021 at 8:21 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Add entry for fixed core clock P0_DIV2 and assign LAST_DT_CORE_CLK > to R9A07G044_LAST_CORE_CLK. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/clk/renesas/r9a07g044-cpg.c > +++ b/drivers/clk/renesas/r9a07g044-cpg.c > @@ -16,7 +16,7 @@ > > enum clk_ids { > /* Core Clock Outputs exported to DT */ > - LAST_DT_CORE_CLK = R9A07G044_OSCCLK, > + LAST_DT_CORE_CLK = R9A07G044_LAST_CORE_CLK,
Please use R9A07G044_CLK_P0_DIV2 instead.
> > /* External Input Clocks */ > CLK_EXTAL, > @@ -77,6 +77,7 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { > DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1), > DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A, > dtable_1_32, CLK_DIVIDER_HIWORD_MASK), > + DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2), > DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1), > DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, > DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
The rest looks good to me.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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