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    Subject[PATCH 4/6] clk: renesas: r9a07g044-cpg: Add entry for fixed clock P0_DIV2
    Date
    Add entry for fixed core clock P0_DIV2 and assign LAST_DT_CORE_CLK
    to R9A07G044_LAST_CORE_CLK.

    Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
    Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
    ---
    drivers/clk/renesas/r9a07g044-cpg.c | 3 ++-
    1 file changed, 2 insertions(+), 1 deletion(-)

    diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
    index 78fae93cf249..0876df9c286d 100644
    --- a/drivers/clk/renesas/r9a07g044-cpg.c
    +++ b/drivers/clk/renesas/r9a07g044-cpg.c
    @@ -16,7 +16,7 @@

    enum clk_ids {
    /* Core Clock Outputs exported to DT */
    - LAST_DT_CORE_CLK = R9A07G044_OSCCLK,
    + LAST_DT_CORE_CLK = R9A07G044_LAST_CORE_CLK,

    /* External Input Clocks */
    CLK_EXTAL,
    @@ -77,6 +77,7 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
    DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
    DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
    dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
    + DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
    DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
    DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
    DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
    --
    2.17.1
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