| Date | Wed, 9 Jun 2021 19:47:02 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH Part1 RFC v3 09/22] x86/compressed: Register GHCB memory when SEV-SNP is active |
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On Wed, Jun 02, 2021 at 09:04:03AM -0500, Brijesh Singh wrote: > diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h > index 1424b8ffde0b..ae99a8a756fe 100644 > --- a/arch/x86/include/asm/sev-common.h > +++ b/arch/x86/include/asm/sev-common.h > @@ -75,6 +75,17 @@ > #define GHCB_MSR_PSC_ERROR_POS 32 > #define GHCB_MSR_PSC_RESP_VAL(val) ((val) >> GHCB_MSR_PSC_ERROR_POS) > > +/* GHCB GPA Register */ > +#define GHCB_MSR_GPA_REG_REQ 0x012 > +#define GHCB_MSR_GPA_REG_VALUE_POS 12 > +#define GHCB_MSR_GPA_REG_GFN_MASK GENMASK_ULL(51, 0) > +#define GHCB_MSR_GPA_REQ_GFN_VAL(v) \ > + (((unsigned long)((v) & GHCB_MSR_GPA_REG_GFN_MASK) << GHCB_MSR_GPA_REG_VALUE_POS)| \ > + GHCB_MSR_GPA_REG_REQ) > + > +#define GHCB_MSR_GPA_REG_RESP 0x013 > +#define GHCB_MSR_GPA_REG_RESP_VAL(v) ((v) >> GHCB_MSR_GPA_REG_VALUE_POS) > +
Can we pls pay attention to having those REQuests sorted by their number, like in the GHCB spec, for faster finding?
-- Regards/Gruss, Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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