Messages in this thread | | | Subject | Re: [PATCH RESEND] clk: vc5: fix output disabling when enabling a FOD | From | Stephen Boyd <> | Date | Tue, 08 Jun 2021 17:53:39 -0700 |
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Quoting Luca Ceresoli (2021-05-27 14:16:47) > On 5P49V6965, when an output is enabled we enable the corresponding > FOD. When this happens for the first time, and specifically when writing > register VC5_OUT_DIV_CONTROL in vc5_clk_out_prepare(), all other outputs > are stopped for a short time and then restarted. > > According to Renesas support this is intended: "The reason for that is VC6E > has synced up all output function". > > This behaviour can be disabled at least on VersaClock 6E devices, of which > only the 5P49V6965 is currently implemented by this driver. This requires > writing bit 7 (bypass_sync{1..4}) in register 0x20..0x50. Those registers > are named "Unused Factory Reserved Register", and the bits are documented > as "Skip VDDO<N> verification", which does not clearly explain the relation > to FOD sync. However according to Renesas support as well as my testing > setting this bit does prevent disabling of all clock outputs when enabling > a FOD. > > See "VersaClock ® 6E Family Register Descriptions and Programming Guide" > (August 30, 2018), Table 116 "Power Up VDD check", page 58: > https://www.renesas.com/us/en/document/mau/versaclock-6e-family-register-descriptions-and-programming-guide > > Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> > Reviewed-by: Adam Ford <aford173@gmail.com> > > ---
Applied to clk-next
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