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    Subject[PATCH 5.12 038/161] net/mlx5: DR, Create multi-destination flow table with level less than 64
    Date
    From: Yevgeny Kliteynik <kliteyn@nvidia.com>

    [ Upstream commit 216214c64a8c1cb9078c2c0aec7bb4a2f8e75397 ]

    Flow table that contains flow pointing to multiple flow tables or multiple
    TIRs must have a level lower than 64. In our case it applies to muli-
    destination flow table.
    Fix the level of the created table to comply with HW Spec definitions, and
    still make sure that its level lower than SW-owned tables, so that it
    would be possible to point from the multi-destination FW table to SW
    tables.

    Fixes: 34583beea4b7 ("net/mlx5: DR, Create multi-destination table for SW-steering use")
    Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
    Reviewed-by: Alex Vesker <valex@nvidia.com>
    Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/net/ethernet/mellanox/mlx5/core/steering/dr_fw.c | 3 ++-
    include/linux/mlx5/mlx5_ifc.h | 2 ++
    2 files changed, 4 insertions(+), 1 deletion(-)

    diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_fw.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_fw.c
    index 1fbcd012bb85..7ccfd40586ce 100644
    --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_fw.c
    +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_fw.c
    @@ -112,7 +112,8 @@ int mlx5dr_fw_create_md_tbl(struct mlx5dr_domain *dmn,
    int ret;

    ft_attr.table_type = MLX5_FLOW_TABLE_TYPE_FDB;
    - ft_attr.level = dmn->info.caps.max_ft_level - 2;
    + ft_attr.level = min_t(int, dmn->info.caps.max_ft_level - 2,
    + MLX5_FT_MAX_MULTIPATH_LEVEL);
    ft_attr.reformat_en = reformat_req;
    ft_attr.decap_en = reformat_req;

    diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
    index 9c68b2da14c6..e5a4c68093fc 100644
    --- a/include/linux/mlx5/mlx5_ifc.h
    +++ b/include/linux/mlx5/mlx5_ifc.h
    @@ -1260,6 +1260,8 @@ enum mlx5_fc_bulk_alloc_bitmask {

    #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))

    +#define MLX5_FT_MAX_MULTIPATH_LEVEL 63
    +
    enum {
    MLX5_STEERING_FORMAT_CONNECTX_5 = 0,
    MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
    --
    2.30.2


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