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    Subject[PATCH 4/6] arm64: dts: mt8183: Add the mmsys reset bit to reset the dsi0
    Date
    Reset the DSI hardware is needed to prevent different settings between
    the bootloader and the kernel.

    While here, also remove the undocumented and also not used
    'mediatek,syscon-dsi' property.

    Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
    ---

    arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 ++-
    include/dt-bindings/reset/mt8183-resets.h | 3 +++
    2 files changed, 5 insertions(+), 1 deletion(-)

    diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
    index 085e2c96b5f4..2d02365633c3 100644
    --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
    +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
    @@ -1286,6 +1286,7 @@ mmsys: syscon@14000000 {
    compatible = "mediatek,mt8183-mmsys", "syscon";
    reg = <0 0x14000000 0 0x1000>;
    #clock-cells = <1>;
    + #reset-cells = <1>;
    mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
    <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
    mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
    @@ -1400,11 +1401,11 @@ dsi0: dsi@14014000 {
    reg = <0 0x14014000 0 0x1000>;
    interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
    power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
    - mediatek,syscon-dsi = <&mmsys 0x140>;
    clocks = <&mmsys CLK_MM_DSI0_MM>,
    <&mmsys CLK_MM_DSI0_IF>,
    <&mipi_tx0>;
    clock-names = "engine", "digital", "hs";
    + resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
    phys = <&mipi_tx0>;
    phy-names = "dphy";
    };
    diff --git a/include/dt-bindings/reset/mt8183-resets.h b/include/dt-bindings/reset/mt8183-resets.h
    index a1bbd41e0d12..48c5d2de0a38 100644
    --- a/include/dt-bindings/reset/mt8183-resets.h
    +++ b/include/dt-bindings/reset/mt8183-resets.h
    @@ -80,6 +80,9 @@

    #define MT8183_INFRACFG_SW_RST_NUM 128

    +/* MMSYS resets */
    +#define MT8183_MMSYS_SW0_RST_B_DISP_DSI0 25
    +
    #define MT8183_TOPRGU_MM_SW_RST 1
    #define MT8183_TOPRGU_MFG_SW_RST 2
    #define MT8183_TOPRGU_VENC_SW_RST 3
    --
    2.30.2
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