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Subject[PATCH v6 04/11] clk: Ingenic: Fix problem of MAC clock in Ingenic X1000 and X1830.
Date
X1000 and X1830 have two MAC related clocks, one is MACPHY, which is
controlled by MACCDR register, the other is MAC, which is controlled
by the MAC bit in the CLKGR register (with CLK_AHB2 as the parent).
The original driver mistakenly mixed the two clocks together.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---

Notes:
v1->v2:
1.Add MACPHY and I2S for X1000, and add MACPHY for X1830.
2.Add Paul Cercueil's Reviewed-by and Rob Herring's Acked-by.

v2->v3:
No change.

v3->v4:
No change.

v4->v5:
Add CIM, AIC, DMIC for X1000, and add CIM, AIC, DMIC, I2S for X1830.

v5->v6:
No change.

drivers/clk/ingenic/x1000-cgu.c | 11 ++++++++---
drivers/clk/ingenic/x1830-cgu.c | 11 ++++++++---
2 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c
index 9aa20b5..53e5fe0 100644
--- a/drivers/clk/ingenic/x1000-cgu.c
+++ b/drivers/clk/ingenic/x1000-cgu.c
@@ -296,12 +296,11 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
.gate = { CGU_REG_CLKGR, 31 },
},

- [X1000_CLK_MAC] = {
- "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
+ [X1000_CLK_MACPHY] = {
+ "mac_phy", CGU_CLK_MUX | CGU_CLK_DIV,
.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL },
.mux = { CGU_REG_MACCDR, 31, 1 },
.div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 },
- .gate = { CGU_REG_CLKGR, 25 },
},

[X1000_CLK_LCD] = {
@@ -452,6 +451,12 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
.gate = { CGU_REG_CLKGR, 21 },
},
+
+ [X1000_CLK_MAC] = {
+ "mac", CGU_CLK_GATE,
+ .parents = { X1000_CLK_AHB2 },
+ .gate = { CGU_REG_CLKGR, 25 },
+ },
};

static void __init x1000_cgu_init(struct device_node *np)
diff --git a/drivers/clk/ingenic/x1830-cgu.c b/drivers/clk/ingenic/x1830-cgu.c
index 950aee2..59342bc 100644
--- a/drivers/clk/ingenic/x1830-cgu.c
+++ b/drivers/clk/ingenic/x1830-cgu.c
@@ -270,13 +270,12 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = {
.gate = { CGU_REG_CLKGR0, 31 },
},

- [X1830_CLK_MAC] = {
- "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
+ [X1830_CLK_MACPHY] = {
+ "mac_phy", CGU_CLK_MUX | CGU_CLK_DIV,
.parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL,
X1830_CLK_VPLL, X1830_CLK_EPLL },
.mux = { CGU_REG_MACCDR, 30, 2 },
.div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 },
- .gate = { CGU_REG_CLKGR1, 4 },
},

[X1830_CLK_LCD] = {
@@ -428,6 +427,12 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = {
.gate = { CGU_REG_CLKGR1, 1 },
},

+ [X1830_CLK_MAC] = {
+ "mac", CGU_CLK_GATE,
+ .parents = { X1830_CLK_AHB2 },
+ .gate = { CGU_REG_CLKGR1, 4 },
+ },
+
[X1830_CLK_OST] = {
"ost", CGU_CLK_GATE,
.parents = { X1830_CLK_EXCLK, -1, -1, -1 },
--
2.7.4
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