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    Subjectdrivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_3_0_2_sh_mask.h:9248:111: warning: initialized field overwritten
    Hi Bhawanpreet,

    FYI, the error/warning still remains.

    tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
    head: 625acffd7ae2c52898d249e6c5c39f348db0d8df
    commit: 9713158cb2a918c3f6f5522eed23cdeb61f22e75 drm/amdgpu: Add and use seperate reg headers for dcn302
    date: 8 months ago
    config: i386-randconfig-r024-20210627 (attached as .config)
    compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
    reproduce (this is a W=1 build):
    # https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9713158cb2a918c3f6f5522eed23cdeb61f22e75
    git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
    git fetch --no-tags linus master
    git checkout 9713158cb2a918c3f6f5522eed23cdeb61f22e75
    # save the attached .config to linux build tree
    make W=1 ARCH=i386

    If you fix the issue, kindly add following tag as appropriate
    Reported-by: kernel test robot <lkp@intel.com>

    All warnings (new ones prefixed by >>):

    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:306:19: note: in expansion of macro 'BASE_INNER'
    306 | #define BASE(seg) BASE_INNER(seg)
    | ^~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:315:15: note: in expansion of macro 'BASE'
    315 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
    | ^~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dio_stream_encoder.h:105:2: note: in expansion of macro 'SRI'
    105 | SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
    | ^~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:502:12: note: in expansion of macro 'SE_DCN3_REG_LIST'
    502 | [id] = { SE_DCN3_REG_LIST(id) }
    | ^~~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:509:3: note: in expansion of macro 'stream_enc_regs'
    509 | stream_enc_regs(4)
    | ^~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../include/dimgrey_cavefish_ip_offset.h:365:52: warning: initialized field overwritten [-Woverride-init]
    365 | #define DCN_BASE__INST0_SEG2 0x000034C0
    | ^~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:304:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2'
    304 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
    | ^~~~~~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:306:19: note: in expansion of macro 'BASE_INNER'
    306 | #define BASE(seg) BASE_INNER(seg)
    | ^~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:315:15: note: in expansion of macro 'BASE'
    315 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
    | ^~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dio_stream_encoder.h:106:2: note: in expansion of macro 'SRI'
    106 | SRI(DIG_FE_CNTL, DIG, id), \
    | ^~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:502:12: note: in expansion of macro 'SE_DCN3_REG_LIST'
    502 | [id] = { SE_DCN3_REG_LIST(id) }
    | ^~~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:509:3: note: in expansion of macro 'stream_enc_regs'
    509 | stream_enc_regs(4)
    | ^~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../include/dimgrey_cavefish_ip_offset.h:365:52: note: (near initialization for 'stream_enc_regs[4].DIG_FE_CNTL')
    365 | #define DCN_BASE__INST0_SEG2 0x000034C0
    | ^~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:304:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2'
    304 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
    | ^~~~~~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:306:19: note: in expansion of macro 'BASE_INNER'
    306 | #define BASE(seg) BASE_INNER(seg)
    | ^~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:315:15: note: in expansion of macro 'BASE'
    315 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
    | ^~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dio_stream_encoder.h:106:2: note: in expansion of macro 'SRI'
    106 | SRI(DIG_FE_CNTL, DIG, id), \
    | ^~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:502:12: note: in expansion of macro 'SE_DCN3_REG_LIST'
    502 | [id] = { SE_DCN3_REG_LIST(id) }
    | ^~~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:509:3: note: in expansion of macro 'stream_enc_regs'
    509 | stream_enc_regs(4)
    | ^~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../include/dimgrey_cavefish_ip_offset.h:365:52: warning: initialized field overwritten [-Woverride-init]
    365 | #define DCN_BASE__INST0_SEG2 0x000034C0
    | ^~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:304:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2'
    304 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
    | ^~~~~~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:306:19: note: in expansion of macro 'BASE_INNER'
    306 | #define BASE(seg) BASE_INNER(seg)
    | ^~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:309:15: note: in expansion of macro 'BASE'
    309 | .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
    | ^~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:170:2: note: in expansion of macro 'SR'
    170 | SR(DCFCLK_CNTL), \
    | ^~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:424:2: note: in expansion of macro 'HWSEQ_DCN_REG_LIST'
    424 | HWSEQ_DCN_REG_LIST(), \
    | ^~~~~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:585:3: note: in expansion of macro 'HWSEQ_DCN302_REG_LIST'
    585 | HWSEQ_DCN302_REG_LIST()
    | ^~~~~~~~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../include/dimgrey_cavefish_ip_offset.h:365:52: note: (near initialization for 'hwseq_reg.DCFCLK_CNTL')
    365 | #define DCN_BASE__INST0_SEG2 0x000034C0
    | ^~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:304:25: note: in expansion of macro 'DCN_BASE__INST0_SEG2'
    304 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
    | ^~~~~~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:306:19: note: in expansion of macro 'BASE_INNER'
    306 | #define BASE(seg) BASE_INNER(seg)
    | ^~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:309:15: note: in expansion of macro 'BASE'
    309 | .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
    | ^~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:170:2: note: in expansion of macro 'SR'
    170 | SR(DCFCLK_CNTL), \
    | ^~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:424:2: note: in expansion of macro 'HWSEQ_DCN_REG_LIST'
    424 | HWSEQ_DCN_REG_LIST(), \
    | ^~~~~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:585:3: note: in expansion of macro 'HWSEQ_DCN302_REG_LIST'
    585 | HWSEQ_DCN302_REG_LIST()
    | ^~~~~~~~~~~~~~~~~~~~~
    In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:64:
    >> drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_3_0_2_sh_mask.h:9248:111: warning: initialized field overwritten [-Woverride-init]
    9248 | #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
    | ^~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:251:16: note: in expansion of macro 'HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT'
    251 | .field_name = reg_name ## __ ## field_name ## post_fix
    | ^~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:404:2: note: in expansion of macro 'HUBP_SF'
    404 | HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
    | ^~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hubp.h:191:2: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN_VM'
    191 | HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
    | ^~~~~~~~~~~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:621:3: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN30'
    621 | HUBP_MASK_SH_LIST_DCN30(__SHIFT)
    | ^~~~~~~~~~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_3_0_2_sh_mask.h:9248:111: note: (near initialization for 'hubp_shift.REFCYC_PER_REQ_DELIVERY')
    9248 | #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
    | ^~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:251:16: note: in expansion of macro 'HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT'
    251 | .field_name = reg_name ## __ ## field_name ## post_fix
    | ^~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:404:2: note: in expansion of macro 'HUBP_SF'
    404 | HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
    | ^~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hubp.h:191:2: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN_VM'
    191 | HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
    | ^~~~~~~~~~~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:621:3: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN30'
    621 | HUBP_MASK_SH_LIST_DCN30(__SHIFT)
    | ^~~~~~~~~~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_3_0_2_sh_mask.h:9249:111: warning: initialized field overwritten [-Woverride-init]
    9249 | #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
    | ^~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:251:16: note: in expansion of macro 'HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT'
    251 | .field_name = reg_name ## __ ## field_name ## post_fix
    | ^~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:405:2: note: in expansion of macro 'HUBP_SF'
    405 | HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
    | ^~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hubp.h:191:2: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN_VM'
    191 | HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
    | ^~~~~~~~~~~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:621:3: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN30'
    621 | HUBP_MASK_SH_LIST_DCN30(__SHIFT)
    | ^~~~~~~~~~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_3_0_2_sh_mask.h:9249:111: note: (near initialization for 'hubp_shift.QoS_LEVEL_FIXED')
    9249 | #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
    | ^~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:251:16: note: in expansion of macro 'HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT'
    251 | .field_name = reg_name ## __ ## field_name ## post_fix
    | ^~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:405:2: note: in expansion of macro 'HUBP_SF'
    405 | HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
    | ^~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hubp.h:191:2: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN_VM'
    191 | HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
    | ^~~~~~~~~~~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:621:3: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN30'
    621 | HUBP_MASK_SH_LIST_DCN30(__SHIFT)
    | ^~~~~~~~~~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_3_0_2_sh_mask.h:9250:111: warning: initialized field overwritten [-Woverride-init]
    9250 | #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
    | ^~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:251:16: note: in expansion of macro 'HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT'
    251 | .field_name = reg_name ## __ ## field_name ## post_fix
    | ^~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:406:2: note: in expansion of macro 'HUBP_SF'
    406 | HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
    | ^~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hubp.h:191:2: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN_VM'
    191 | HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
    | ^~~~~~~~~~~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:621:3: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN30'
    621 | HUBP_MASK_SH_LIST_DCN30(__SHIFT)
    | ^~~~~~~~~~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_3_0_2_sh_mask.h:9250:111: note: (near initialization for 'hubp_shift.QoS_RAMP_DISABLE')
    9250 | #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
    | ^~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:251:16: note: in expansion of macro 'HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT'
    251 | .field_name = reg_name ## __ ## field_name ## post_fix
    | ^~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:406:2: note: in expansion of macro 'HUBP_SF'
    406 | HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
    | ^~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hubp.h:191:2: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN_VM'
    191 | HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
    | ^~~~~~~~~~~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:621:3: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN30'
    621 | HUBP_MASK_SH_LIST_DCN30(__SHIFT)
    | ^~~~~~~~~~~~~~~~~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_3_0_2_sh_mask.h:9255:111: warning: initialized field overwritten [-Woverride-init]
    9255 | #define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
    | ^~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:251:16: note: in expansion of macro 'HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT'
    251 | .field_name = reg_name ## __ ## field_name ## post_fix
    | ^~~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/../dcn10/dcn10_hubp.h:407:2: note: in expansion of macro 'HUBP_SF'
    407 | HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh)
    | ^~~~~~~
    drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hubp.h:191:2: note: in expansion of macro 'HUBP_MASK_SH_LIST_DCN_VM'
    191 | HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\


    vim +9248 drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_3_0_2_sh_mask.h

    9028
    9029
    9030 // addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
    9031 //HUBPREQ0_DCSURF_SURFACE_PITCH
    9032 #define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0
    9033 #define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10
    9034 #define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL
    9035 #define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L
    9036 //HUBPREQ0_DCSURF_SURFACE_PITCH_C
    9037 #define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0
    9038 #define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10
    9039 #define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL
    9040 #define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L
    9041 //HUBPREQ0_VMID_SETTINGS_0
    9042 #define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT 0x0
    9043 #define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK 0x0000000FL
    9044 //HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS
    9045 #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0
    9046 #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
    9047 //HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
    9048 #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
    9049 #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
    9050 //HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C
    9051 #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0
    9052 #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
    9053 //HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
    9054 #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
    9055 #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
    9056 //HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS
    9057 #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0
    9058 #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
    9059 //HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
    9060 #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
    9061 #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
    9062 //HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C
    9063 #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0
    9064 #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
    9065 //HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
    9066 #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
    9067 #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
    9068 //HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS
    9069 #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0
    9070 #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
    9071 //HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
    9072 #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0
    9073 #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
    9074 //HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
    9075 #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0
    9076 #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
    9077 //HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
    9078 #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
    9079 #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
    9080 //HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS
    9081 #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0
    9082 #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL
    9083 //HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
    9084 #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0
    9085 #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL
    9086 //HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
    9087 #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0
    9088 #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL
    9089 //HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
    9090 #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
    9091 #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
    9092 //HUBPREQ0_DCSURF_SURFACE_CONTROL
    9093 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0
    9094 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1
    9095 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x2
    9096 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4
    9097 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x5
    9098 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8
    9099 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9
    9100 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0xa
    9101 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc
    9102 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xd
    9103 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10
    9104 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11
    9105 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12
    9106 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13
    9107 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L
    9108 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L
    9109 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x0000000CL
    9110 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L
    9111 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00000060L
    9112 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L
    9113 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L
    9114 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x00000C00L
    9115 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L
    9116 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x00006000L
    9117 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L
    9118 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L
    9119 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L
    9120 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L
    9121 //HUBPREQ0_DCSURF_FLIP_CONTROL
    9122 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0
    9123 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1
    9124 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4
    9125 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8
    9126 #define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9
    9127 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc
    9128 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10
    9129 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11
    9130 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12
    9131 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14
    9132 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L
    9133 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L
    9134 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L
    9135 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L
    9136 #define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L
    9137 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L
    9138 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L
    9139 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L
    9140 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L
    9141 #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L
    9142 //HUBPREQ0_DCSURF_FLIP_CONTROL2
    9143 #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0
    9144 #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8
    9145 #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9
    9146 #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa
    9147 #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc
    9148 #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL
    9149 #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L
    9150 #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L
    9151 #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L
    9152 #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L
    9153 //HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT
    9154 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0
    9155 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1
    9156 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2
    9157 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3
    9158 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8
    9159 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9
    9160 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10
    9161 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11
    9162 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12
    9163 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13
    9164 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L
    9165 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L
    9166 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L
    9167 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L
    9168 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L
    9169 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L
    9170 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L
    9171 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L
    9172 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L
    9173 #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L
    9174 //HUBPREQ0_DCSURF_SURFACE_INUSE
    9175 #define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0
    9176 #define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL
    9177 //HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH
    9178 #define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0
    9179 #define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c
    9180 #define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL
    9181 #define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L
    9182 //HUBPREQ0_DCSURF_SURFACE_INUSE_C
    9183 #define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0
    9184 #define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL
    9185 //HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C
    9186 #define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0
    9187 #define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c
    9188 #define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
    9189 #define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L
    9190 //HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE
    9191 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0
    9192 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL
    9193 //HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
    9194 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0
    9195 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c
    9196 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL
    9197 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L
    9198 //HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C
    9199 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0
    9200 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL
    9201 //HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
    9202 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0
    9203 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c
    9204 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL
    9205 #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L
    9206 //HUBPREQ0_DCN_EXPANSION_MODE
    9207 #define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0
    9208 #define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2
    9209 #define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4
    9210 #define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6
    9211 #define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L
    9212 #define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL
    9213 #define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L
    9214 #define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L
    9215 //HUBPREQ0_DCN_TTU_QOS_WM
    9216 #define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0
    9217 #define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10
    9218 #define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL
    9219 #define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L
    9220 //HUBPREQ0_DCN_GLOBAL_TTU_CNTL
    9221 #define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0
    9222 #define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b
    9223 #define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c
    9224 #define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL
    9225 #define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L
    9226 #define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L
    9227 //HUBPREQ0_DCN_SURF0_TTU_CNTL0
    9228 #define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
    9229 #define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
    9230 #define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
    9231 #define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
    9232 #define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
    9233 #define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
    9234 //HUBPREQ0_DCN_SURF0_TTU_CNTL1
    9235 #define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
    9236 #define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
    9237 //HUBPREQ0_DCN_SURF1_TTU_CNTL0
    9238 #define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
    9239 #define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
    9240 #define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
    9241 #define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
    9242 #define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
    9243 #define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
    9244 //HUBPREQ0_DCN_SURF1_TTU_CNTL1
    9245 #define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
    9246 #define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
    9247 //HUBPREQ0_DCN_CUR0_TTU_CNTL0
    > 9248 #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
    9249 #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
    9250 #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
    9251 #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
    9252 #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
    9253 #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
    9254 //HUBPREQ0_DCN_CUR0_TTU_CNTL1
    9255 #define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
    9256 #define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
    9257 //HUBPREQ0_DCN_CUR1_TTU_CNTL0
    9258 #define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0
    9259 #define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18
    9260 #define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c
    9261 #define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL
    9262 #define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L
    9263 #define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L
    9264 //HUBPREQ0_DCN_CUR1_TTU_CNTL1
    9265 #define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0
    9266 #define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL
    9267 //HUBPREQ0_DCN_DMDATA_VM_CNTL
    9268 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT 0x0
    9269 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT 0x10
    9270 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT 0x14
    9271 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT 0x18
    9272 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT 0x19
    9273 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT 0x1a
    9274 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT 0x1f
    9275 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK 0x0000FFFFL
    9276 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK 0x000F0000L
    9277 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK 0x00100000L
    9278 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK 0x01000000L
    9279 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK 0x02000000L
    9280 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK 0x04000000L
    9281 #define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK 0x80000000L
    9282 //HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
    9283 #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0
    9284 #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL
    9285 //HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
    9286 #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0
    9287 #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL
    9288 //HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL
    9289 #define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
    9290 #define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
    9291 #define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
    9292 #define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
    9293 #define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L
    9294 #define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L
    9295 #define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L
    9296 #define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L
    9297 //HUBPREQ0_BLANK_OFFSET_0
    9298 #define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0
    9299 #define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10
    9300 #define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL
    9301 #define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L
    9302 //HUBPREQ0_BLANK_OFFSET_1
    9303 #define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0
    9304 #define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL
    9305 //HUBPREQ0_DST_DIMENSIONS
    9306 #define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0
    9307 #define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL
    9308 //HUBPREQ0_DST_AFTER_SCALER
    9309 #define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0
    9310 #define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10
    9311 #define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL
    9312 #define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L
    9313 //HUBPREQ0_PREFETCH_SETTINGS
    9314 #define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0
    9315 #define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18
    9316 #define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL
    9317 #define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L
    9318 //HUBPREQ0_PREFETCH_SETTINGS_C
    9319 #define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0
    9320 #define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL
    9321 //HUBPREQ0_VBLANK_PARAMETERS_0
    9322 #define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0
    9323 #define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8
    9324 #define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL
    9325 #define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L
    9326 //HUBPREQ0_VBLANK_PARAMETERS_1
    9327 #define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0
    9328 #define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL
    9329 //HUBPREQ0_VBLANK_PARAMETERS_2
    9330 #define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0
    9331 #define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL
    9332 //HUBPREQ0_VBLANK_PARAMETERS_3
    9333 #define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0
    9334 #define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL
    9335 //HUBPREQ0_VBLANK_PARAMETERS_4
    9336 #define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0
    9337 #define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL
    9338 //HUBPREQ0_FLIP_PARAMETERS_0
    9339 #define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0
    9340 #define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8
    9341 #define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL
    9342 #define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L
    9343 //HUBPREQ0_FLIP_PARAMETERS_1
    9344 #define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0
    9345 #define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL
    9346 //HUBPREQ0_FLIP_PARAMETERS_2
    9347 #define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0
    9348 #define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL
    9349 //HUBPREQ0_NOM_PARAMETERS_0
    9350 #define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0
    9351 #define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL
    9352 //HUBPREQ0_NOM_PARAMETERS_1
    9353 #define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0
    9354 #define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL
    9355 //HUBPREQ0_NOM_PARAMETERS_2
    9356 #define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0
    9357 #define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL
    9358 //HUBPREQ0_NOM_PARAMETERS_3
    9359 #define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0
    9360 #define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL
    9361 //HUBPREQ0_NOM_PARAMETERS_4
    9362 #define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0
    9363 #define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL
    9364 //HUBPREQ0_NOM_PARAMETERS_5
    9365 #define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0
    9366 #define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL
    9367 //HUBPREQ0_NOM_PARAMETERS_6
    9368 #define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0
    9369 #define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL
    9370 //HUBPREQ0_NOM_PARAMETERS_7
    9371 #define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0
    9372 #define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL
    9373 //HUBPREQ0_PER_LINE_DELIVERY_PRE
    9374 #define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0
    9375 #define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10
    9376 #define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL
    9377 #define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L
    9378 //HUBPREQ0_PER_LINE_DELIVERY
    9379 #define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0
    9380 #define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10
    9381 #define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL
    9382 #define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L
    9383 //HUBPREQ0_CURSOR_SETTINGS
    9384 #define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0
    9385 #define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8
    9386 #define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10
    9387 #define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18
    9388 #define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL
    9389 #define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L
    9390 #define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L
    9391 #define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L
    9392 //HUBPREQ0_REF_FREQ_TO_PIX_FREQ
    9393 #define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0
    9394 #define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL
    9395 //HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT
    9396 #define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0
    9397 #define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL
    9398 //HUBPREQ0_HUBPREQ_MEM_PWR_CTRL
    9399 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0
    9400 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2
    9401 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4
    9402 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6
    9403 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8
    9404 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa
    9405 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc
    9406 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe
    9407 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L
    9408 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L
    9409 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L
    9410 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L
    9411 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L
    9412 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L
    9413 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L
    9414 #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L
    9415 //HUBPREQ0_HUBPREQ_MEM_PWR_STATUS
    9416 #define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0
    9417 #define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2
    9418 #define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4
    9419 #define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6
    9420 #define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L
    9421 #define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL
    9422 #define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L
    9423 #define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L
    9424 //HUBPREQ0_VBLANK_PARAMETERS_5
    9425 #define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0
    9426 #define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL
    9427 //HUBPREQ0_VBLANK_PARAMETERS_6
    9428 #define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0
    9429 #define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL
    9430 //HUBPREQ0_FLIP_PARAMETERS_3
    9431 #define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0
    9432 #define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL
    9433 //HUBPREQ0_FLIP_PARAMETERS_4
    9434 #define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0
    9435 #define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL
    9436 //HUBPREQ0_FLIP_PARAMETERS_5
    9437 #define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0
    9438 #define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL
    9439 //HUBPREQ0_FLIP_PARAMETERS_6
    9440 #define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0
    9441 #define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL
    9442
    9443

    ---
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