Messages in this thread | | | Subject | Re: [PATCH v4 4/7] clk: st: clkgen-pll: embed soc clock outputs within compatible data | From | Stephen Boyd <> | Date | Sun, 27 Jun 2021 19:54:59 -0700 |
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Quoting Alain Volmat (2021-03-31 13:16:29) > In order to avoid relying on the old style description via the DT > clock-output-names, add compatible data describing the flexgen > outputs clocks for all STiH407/STiH410 and STiH418 SOCs. > > In order to ease transition between the two methods, this commit > introduce the new compatible without removing the old method. > Once DTs will be fixed, the method relying on DT clock-output-names > will be removed from this driver as well as old compatibles. > > Signed-off-by: Alain Volmat <avolmat@me.com> > Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> > ---
Applied to clk-next
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