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SubjectRe: [PATCH v5 2/3] clk: lmk04832: add support for digital delay
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Quoting Liam Beguin (2021-04-22 17:40:56)
> From: Liam Beguin <lvb@xiphos.com>
>
> The digital delay allows outputs to be delayed from 8 to 1023 VCO
> cycles. The delay step can be as small as half the period of the clock
> distribution path. For example, a 3.2-GHz VCO frequency results in
> 156.25-ps steps. The digital delay value takes effect on the clock
> output phase after a SYNC event.
>
> This is required to support JESD204B subclass 1.
>
> Signed-off-by: Liam Beguin <lvb@xiphos.com>
> ---

Applied to clk-next

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