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SubjectRe: [PATCH 1/3] dt-bindings: phy: mediatek: tphy: add support hardware version 3
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On Wed, 2021-06-16 at 17:28 -0600, Rob Herring wrote:
> On Fri, Jun 04, 2021 at 03:31:18PM +0800, Chunfeng Yun wrote:
> > The PHYA architecture is updated, and doesn't support slew rate
> > calibration anymore on 7nm or advanced process, add a new version
> > number to support it.
> > Note: the FreqMeter bank is not used but reserved.
> >
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> > .../devicetree/bindings/phy/mediatek,tphy.yaml | 14 +++++++++-----
> > 1 file changed, 9 insertions(+), 5 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
> > index b8a7651a3d9a..939c09296b5f 100644
> > --- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
> > @@ -15,7 +15,7 @@ description: |
> > controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
> >
> > Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
> > - T-PHY V2 (mt2712) when works on USB mode:
> > + T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
> > -----------------------------------
> > Version 1:
> > port offset bank
> > @@ -34,7 +34,7 @@ description: |
> > u2 port2 0x1800 U2PHY_COM
> > ...
> >
> > - Version 2:
> > + Version 2/3:
> > port offset bank
> > u2 port0 0x0000 MISC
> > 0x0100 FMREG
> > @@ -59,7 +59,8 @@ description: |
> >
> > SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
> > into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
> > - added on V2.
> > + added on V2; the FMREG bank for slew rate calibration is not used anymore
> > + and reserved on V3;
> >
> > properties:
> > $nodename:
> > @@ -79,8 +80,11 @@ properties:
> > - mediatek,mt2712-tphy
> > - mediatek,mt7629-tphy
> > - mediatek,mt8183-tphy
> > - - mediatek,mt8195-tphy
> > - const: mediatek,generic-tphy-v2
>
> This doesn't look like a good change.
>
> What happens if a DT has the above. It didn't work or didn't support new
> features?
It does not affect function, but will waste some time to calibrate slew
rate on mt8195.

> Please clarify in the commit the implications of changing
> this. Changing a DT to 'mediatek,generic-tphy-v3' will break existing OS
> if it was looking for v2.
On mt8195, it's backward compatible with hw v2, the unused FMREG bank is
reversed, but noop when W/R registers.
>
> > + - items:
> > + - enum:
> > + - mediatek,mt8195-tphy
> > + - const: mediatek,generic-tphy-v3
> > - const: mediatek,mt2701-u3phy
> > deprecated: true
> > - const: mediatek,mt2712-u3phy
> > @@ -91,7 +95,7 @@ properties:
> > description:
> > Register shared by multiple ports, exclude port's private register.
> > It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
> > - T-PHY V2, such as mt2712.
> > + T-PHY V2/V3, such as mt2712.
> > maxItems: 1
> >
> > "#address-cells":
> > --
> > 2.18.0

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