Messages in this thread | | | Date | Tue, 15 Jun 2021 17:43:21 -0600 | From | Rob Herring <> | Subject | Re: [PATCH 1/8] dt-bindings: arm/npcm: Add binding for global control registers (GCR) |
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On Wed, Jun 02, 2021 at 02:03:22PM +0200, Jonathan Neuschäfer wrote: > A nuvoton,*-gcr node is present in nuvoton-common-npcm7xx.dtsi and will > be added to nuvoton-wpcm450.dtsi. It is necessary for the NPCM7xx and > WPCM450 pinctrl drivers, and may later be used to retrieve SoC model and > version information. > > This patch adds a binding to describe this node. > > Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> > --- > .../bindings/arm/npcm/nuvoton,gcr.yaml | 38 +++++++++++++++++++ > 1 file changed, 38 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml > > diff --git a/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml b/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml > new file mode 100644 > index 0000000000000..3174279f7713a > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml > @@ -0,0 +1,38 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/npcm/nuvoton,gcr.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Global Control Registers block in Nuvoton SoCs > + > +maintainers: > + - Jonathan Neuschäfer <j.neuschaefer@gmx.net> > + > +description: | > + The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs > + that expose misc functionality such as chip model and version information or > + pinmux settings. > + > +properties: > + compatible: > + items: > + - enum: > + - nuvoton,wpcm450-gcr > + - nuvoton,npcm750-gcr > + - const: syscon > + - const: simple-mfd
How is this a simple-mfd? There are no child nodes.
> + reg: true > + > +required: > + - compatible > + - reg > + > +additionalProperties: false > + > +examples: > + - | > + gcr: gcr@800000 { > + compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd"; > + reg = <0x800000 0x1000>; > + }; > -- > 2.30.2
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