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SubjectRe: [PATCH] x86/events/amd/iommu: Fix invalid Perf result due to IOMMU PMC power-gating
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Peter,

On 5/4/2021 4:39 PM, Peter Zijlstra wrote:
> On Tue, May 04, 2021 at 01:52:36AM -0500, Suravee Suthikulpanit wrote:
>
>> 2. Since AMD IOMMU PMU does not support interrupt mode, the logic
>> can be simplified to always start counting with value zero,
>> and accumulate the counter value when stopping without the need
>> to keep track and reprogram the counter with the previously read
>> counter value.
>
> This relies on the hardware counter being the full 64bit wide, is it?
>

The HW counter value is 48-bit. Not sure why it needs to be 64-bit?
I might be missing some points here? Could you please describe?

Thanks,
Suravee


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