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SubjectRe: [PATCH V2 0/4] soc: imx: add i.MX BLK-CTL support
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On 03.05.21 16:57, Frieder Schrempf wrote:
> Hi Peng,
>
> On 30.04.21 07:27, Peng Fan (OSS) wrote:
>> From: Peng Fan <peng.fan@nxp.com>
>>
>> V2:
>>   Fix yaml check failure
>>
>> Previously there is an effort from Abel that take BLK-CTL as clock
>> provider, but it turns out that there is A/B lock issue and we are
>> not able resolve that.
>>
>> Per discuss with Lucas and Jacky, we made an agreement that take BLK-CTL
>> as a power domain provider and use GPC's domain as parent, the consumer
>> node take BLK-CTL as power domain input.
>>
>> This patchset has been tested on i.MX8MM EVK board, but one hack
>> is not included in the patchset is that the DISPMIX BLK-CTL
>> MIPI_M/S_RESET
>> not implemented. Per Lucas, we will finally have a MIPI DPHY driver,
>> so fine to leave it.
>
> Thanks for your work. I would like to test this together with the DSIM
> and PHY driver by Michael and Marek. So far the boot hangs when probing
> the DSIM, but I'm not even sure if my DT is correct.
>
> With the DSIM PHY driver (see [1]) in place, the GPR_MIPI_M_RESETN
> should be set correctly, right?

So I found out, that with the hack below applied (taken from Marek's WIP
patches for DSIM support) it seems to work properly.

Therefore I guess this is an issue with the DSIM driver, that somehow
needs to make sure that the proper clocks are enabled at probe time.

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 04564017bfe9..5a9bca805b0c 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -9,6 +9,7 @@
*/

#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
@@ -193,6 +194,7 @@ to_imx_pgc_domain(struct generic_pm_domain *genpd)
static int imx_pgc_power_up(struct generic_pm_domain *genpd)
{
struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
+ unsigned int i;
u32 reg_val;
int ret;

@@ -254,7 +256,14 @@ static int imx_pgc_power_up(struct
generic_pm_domain *genpd)
}

/* Disable reset clocks for all devices in the domain */
- clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
+ //clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
+ for (i = 0; i < domain->num_clks; i++) {
+ /* Keep the DISPMIX active, it is needed by both LCDIF
and MIPI */
+ if (strcmp(__clk_get_name(domain->clks[i].clk),
"disp_root_clk") &&
+ strcmp(__clk_get_name(domain->clks[i].clk),
"disp_axi_root_clk") &&
+ strcmp(__clk_get_name(domain->clks[i].clk),
"disp_apb_root_clk"))
+ clk_disable_unprepare(domain->clks[i].clk);
+ }

return 0;
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