Messages in this thread | | | From | Jerome Brunet <> | Subject | Re: [PATCH] clk: meson: meson8b: Don't use MPLL1 as parent of vclk_in_sel | Date | Mon, 24 May 2021 12:57:58 +0200 |
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On Mon 24 May 2021 at 12:45, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
> MPLL1 is needed for audio output. Drop it from the vclk_in_sel parent > list so we only use the (mutable) vid_pll_final_div tree or one of the > (fixed) FCLK_DIV{3,4,5} clocks.
Are the fixed ones actually needed ?
If the consumer actually lives on the vid_pll only, I'd prefer if you could add CLK_SET_RATE_NOREPARENT and assign the proper parent in DT with `assigned-clock-parents`
> > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > --- > drivers/clk/meson/meson8b.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c > index a844d35b553a..f8bd211db720 100644 > --- a/drivers/clk/meson/meson8b.c > +++ b/drivers/clk/meson/meson8b.c > @@ -1154,6 +1154,10 @@ static struct clk_regmap meson8b_vid_pll_final_div = { > }, > }; > > +/* > + * parent 0x6 is meson8b_mpll1 but we don't use it here because it's reserved > + * for the audio outputs. > + */ > static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = { > &meson8b_vid_pll_final_div.hw, > &meson8b_fclk_div4.hw, > @@ -1161,7 +1165,6 @@ static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = { > &meson8b_fclk_div5.hw, > &meson8b_vid_pll_final_div.hw, > &meson8b_fclk_div7.hw, > - &meson8b_mpll1.hw, > }; > > static struct clk_regmap meson8b_vclk_in_sel = {
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