Messages in this thread | | | Date | Fri, 21 May 2021 10:36:07 +0930 | From | "Andrew Jeffery" <> | Subject | Re: [PATCH v4 3/3] mmc: sdhci-of-aspeed: Configure the SDHCIs as specified by the devicetree. |
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On Thu, 20 May 2021, at 19:43, Steven Lee wrote: > The hardware provides capability configuration registers for each SDHCI > in the global configuration space for the SD controller. Writes to the > global capability registers are mirrored to the capability registers in > the associated SDHCI. Configuration of the capabilities must be written > through the mirror registers prior to initialisation of the SDHCI. > > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
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