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    Subject[PATCH 3/7] clk: stm32: Fix ltdc's clock turn off by clk_disable_unused() after kernel startup
    Date
    From: Dillon Min <dillon.minfei@gmail.com>

    stm32's clk driver register two ltdc gate clk to clk core by
    clk_hw_register_gate() and clk_hw_register_composite()

    first: 'stm32f429_gates[]', clk name is 'ltdc', which no user to use.
    second: 'stm32f429_aux_clk[]', clk name is 'lcd-tft', used by ltdc driver

    both of them point to the same offset of stm32's RCC register. after
    kernel enter console, clk core turn off ltdc's clk as 'stm32f429_gates[]'
    is no one to use. but, actually 'stm32f429_aux_clk[]' is in use.

    Fixes: daf2d117cbca ("clk: stm32f4: Add lcd-tft clock")
    Signed-off-by: Dillon Min <dillon.minfei@gmail.com>
    Acked-by: Stephen Boyd <sboyd@kernel.org>
    Link: https://lore.kernel.org/linux-arm-kernel/1590564453-24499-7-git-send-email-dillon.minfei@gmail.com/
    ---

    This patch was submitted in
    https://lore.kernel.org/lkml/1620990152-19255-1-git-send-email-dillon.minfei@gmail.com/

    drivers/clk/clk-stm32f4.c | 7 +++----
    1 file changed, 3 insertions(+), 4 deletions(-)

    diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
    index 18117ce5ff85..b6ab8c3a7994 100644
    --- a/drivers/clk/clk-stm32f4.c
    +++ b/drivers/clk/clk-stm32f4.c
    @@ -211,7 +211,6 @@ static const struct stm32f4_gate_data stm32f469_gates[] __initconst = {
    { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
    { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
    { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
    - { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
    };

    static const struct stm32f4_gate_data stm32f746_gates[] __initconst = {
    @@ -557,13 +556,13 @@ static const struct clk_div_table post_divr_table[] = {

    #define MAX_POST_DIV 3
    static const struct stm32f4_pll_post_div_data post_div_data[MAX_POST_DIV] = {
    - { CLK_I2SQ_PDIV, PLL_I2S, "plli2s-q-div", "plli2s-q",
    + { CLK_I2SQ_PDIV, PLL_VCO_I2S, "plli2s-q-div", "plli2s-q",
    CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL},

    - { CLK_SAIQ_PDIV, PLL_SAI, "pllsai-q-div", "pllsai-q",
    + { CLK_SAIQ_PDIV, PLL_VCO_SAI, "pllsai-q-div", "pllsai-q",
    CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL },

    - { NO_IDX, PLL_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
    + { NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
    STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table },
    };

    --
    2.7.4
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