Messages in this thread | | | Date | Wed, 7 Apr 2021 18:54:46 +0200 | From | Peter Zijlstra <> | Subject | Re: [PATCH v4 3/4] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 |
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On Wed, Apr 07, 2021 at 05:52:36PM +0200, Peter Zijlstra wrote: > On Wed, Apr 07, 2021 at 04:29:12PM +0200, Christoph Müllner wrote: > > The comparison with sparc64 is not applicable, as sparc64 does not > > have LL/SC instructions. > > Sparc64 has CAS, without hardware fwd progress. It has to do software > backoff for failed CAS in order to do software fwd progress.
Again, the longer answer is that this applies identically to LL/SC and I'm sure we actually have (or had) an architecture in tree that did just that. I just cannot remember which architecture that was.
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