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    Subject[PATCH 3/5] x86/speculation: Introduce SPEC_CTRL_MSR bit for PSFD
    Date
    From: Ramakrishna Saripalli <rk.saripalli@amd.com>

    All AMD processors that support PSF implement a bit in
    SPEC_CTRL MSR (0x48) to disable or enable Predictive Store
    Forwarding.

    Signed-off-by: Ramakrishna Saripalli<rk.saripalli@amd.com>
    ---
    arch/x86/include/asm/msr-index.h | 2 ++
    1 file changed, 2 insertions(+)

    diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
    index 546d6ecf0a35..f569918c8754 100644
    --- a/arch/x86/include/asm/msr-index.h
    +++ b/arch/x86/include/asm/msr-index.h
    @@ -51,6 +51,8 @@
    #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */
    #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */
    #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */
    +#define SPEC_CTRL_PSFD_SHIFT 7
    +#define SPEC_CTRL_PSFD BIT(SPEC_CTRL_PSFD_SHIFT) /* Predictive Store Forwarding Disable */

    #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
    #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */
    --
    2.25.1
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