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    Subject[PATCH v6 20/20] dts: bindings: Document device tree bindings for Arm TRBE
    Date
    Document the device tree bindings for Trace Buffer Extension (TRBE).

    Cc: Anshuman Khandual <anshuman.khandual@arm.com>
    Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
    Cc: Rob Herring <robh@kernel.org>
    Cc: devicetree@vger.kernel.org
    Reviewed-by: Rob Herring <robh@kernel.org>
    Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
    ---
    .../devicetree/bindings/arm/trbe.yaml | 49 +++++++++++++++++++
    MAINTAINERS | 1 +
    2 files changed, 50 insertions(+)
    create mode 100644 Documentation/devicetree/bindings/arm/trbe.yaml

    diff --git a/Documentation/devicetree/bindings/arm/trbe.yaml b/Documentation/devicetree/bindings/arm/trbe.yaml
    new file mode 100644
    index 000000000000..4402d7bfd1fc
    --- /dev/null
    +++ b/Documentation/devicetree/bindings/arm/trbe.yaml
    @@ -0,0 +1,49 @@
    +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
    +# Copyright 2021, Arm Ltd
    +%YAML 1.2
    +---
    +$id: "http://devicetree.org/schemas/arm/trbe.yaml#"
    +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
    +
    +title: ARM Trace Buffer Extensions
    +
    +maintainers:
    + - Anshuman Khandual <anshuman.khandual@arm.com>
    +
    +description: |
    + Arm Trace Buffer Extension (TRBE) is a per CPU component
    + for storing trace generated on the CPU to memory. It is
    + accessed via CPU system registers. The software can verify
    + if it is permitted to use the component by checking the
    + TRBIDR register.
    +
    +properties:
    + $nodename:
    + const: "trbe"
    + compatible:
    + items:
    + - const: arm,trace-buffer-extension
    +
    + interrupts:
    + description: |
    + Exactly 1 PPI must be listed. For heterogeneous systems where
    + TRBE is only supported on a subset of the CPUs, please consult
    + the arm,gic-v3 binding for details on describing a PPI partition.
    + maxItems: 1
    +
    +required:
    + - compatible
    + - interrupts
    +
    +additionalProperties: false
    +
    +examples:
    +
    + - |
    + #include <dt-bindings/interrupt-controller/arm-gic.h>
    +
    + trbe {
    + compatible = "arm,trace-buffer-extension";
    + interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
    + };
    +...
    diff --git a/MAINTAINERS b/MAINTAINERS
    index 2a20a36c724a..471d04bb2d5e 100644
    --- a/MAINTAINERS
    +++ b/MAINTAINERS
    @@ -1762,6 +1762,7 @@ F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
    F: Documentation/devicetree/bindings/arm/coresight-cti.yaml
    F: Documentation/devicetree/bindings/arm/coresight.txt
    F: Documentation/devicetree/bindings/arm/ete.yaml
    +F: Documentation/devicetree/bindings/arm/trbe.yaml
    F: Documentation/trace/coresight/*
    F: drivers/hwtracing/coresight/*
    F: include/dt-bindings/arm/coresight-cti-dt.h
    --
    2.24.1
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