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Subject[PATCH 0/4] soc: imx: add i.MX BLK-CTL support
Date
From: Peng Fan <peng.fan@nxp.com>

Previously there is an effort from Abel that take BLK-CTL as clock
provider, but it turns out that there is A/B lock issue and we are
not able resolve that.

Per discuss with Lucas and Jacky, we made an agreement that take BLK-CTL
as a power domain provider and use GPC's domain as parent, the consumer
node take BLK-CTL as power domain input.

This patchset has been tested on i.MX8MM EVK board, but one hack
is not included in the patchset is that the DISPMIX BLK-CTL MIPI_M/S_RESET
not implemented. Per Lucas, we will finally have a MIPI DPHY driver,
so fine to leave it.

Thanks for Lucas's suggestion, Frieder Schrempf for collecting
all the patches, Abel's previous BLK-CTL work, Jacky Bai on help
debug issues.

Peng Fan (4):
dt-bindings: power: Add defines for i.MX8MM BLK-CTL power domains
Documentation: bindings: clk: Add bindings for i.MX BLK_CTL
soc: imx: Add generic blk-ctl driver
soc: imx: Add blk-ctl driver for i.MX8MM

.../bindings/soc/imx/fsl,imx-blk-ctl.yaml | 73 +++++
drivers/soc/imx/Makefile | 2 +-
drivers/soc/imx/blk-ctl-imx8mm.c | 138 ++++++++
drivers/soc/imx/blk-ctl.c | 303 ++++++++++++++++++
drivers/soc/imx/blk-ctl.h | 76 +++++
include/dt-bindings/power/imx8mm-power.h | 11 +
6 files changed, 602 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml
create mode 100644 drivers/soc/imx/blk-ctl-imx8mm.c
create mode 100644 drivers/soc/imx/blk-ctl.c
create mode 100644 drivers/soc/imx/blk-ctl.h

--
2.30.0

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