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SubjectRe: [v3 1/1] x86/cpufeatures: Implement Predictive Store Forwarding control.
On Thu, Apr 29, 2021 at 09:32:35AM -0500, Saripalli, RK wrote:
> Yes, I agree with his analysis and fixing it.

So you can do this and correct the comment above it to explain why
you're doing the "tmp" thing.

diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index d41b70fe4918..536136e0daa3 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -78,6 +78,8 @@ EXPORT_SYMBOL_GPL(mds_idle_clear);

void __init check_bugs(void)
{
+ u64 tmp = 0;
+
identify_boot_cpu();

/*
@@ -97,7 +99,9 @@ void __init check_bugs(void)
* init code as it is not enumerated and depends on the family.
*/
if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
- rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
+ rdmsrl(MSR_IA32_SPEC_CTRL, tmp);
+
+ x86_spec_ctrl_base |= tmp;

/* Allow STIBP in MSR_SPEC_CTRL if supported */
if (boot_cpu_has(X86_FEATURE_STIBP))
---
and as Tom correctly suggests, set X86_FEATURE_MSR_SPEC_CTRL in
psf_cmdline() so that the above loading of the base value works.

Thx.

--
Regards/Gruss,
Boris.

https://people.kernel.org/tglx/notes-about-netiquette

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