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    Subject[PATCH v1 5/7] mfd: lpc_ich: Switch to generic pci_p2sb_bar()
    Date
    Instead of open coding pci_p2sb_bar() functionality we are going to
    use generic library for that. There one more user of it is coming.

    Besides cleaning up it fixes a potential issue if, by some reason,
    SPI bar is 64-bit.

    Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
    ---
    drivers/mfd/Kconfig | 1 +
    drivers/mfd/lpc_ich.c | 20 ++++++--------------
    2 files changed, 7 insertions(+), 14 deletions(-)

    diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
    index a03de3f7a8ed..c16bec1852e5 100644
    --- a/drivers/mfd/Kconfig
    +++ b/drivers/mfd/Kconfig
    @@ -553,6 +553,7 @@ config LPC_ICH
    tristate "Intel ICH LPC"
    depends on PCI
    select MFD_CORE
    + select PCI_P2SB if X86
    help
    The LPC bridge function of the Intel ICH provides support for
    many functional units. This driver provides needed support for
    diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c
    index 3a19ed57260e..8e9bd6813287 100644
    --- a/drivers/mfd/lpc_ich.c
    +++ b/drivers/mfd/lpc_ich.c
    @@ -42,6 +42,7 @@
    #include <linux/errno.h>
    #include <linux/acpi.h>
    #include <linux/pci.h>
    +#include <linux/pci-p2sb.h>
    #include <linux/mfd/core.h>
    #include <linux/mfd/lpc_ich.h>
    #include <linux/platform_data/itco_wdt.h>
    @@ -69,8 +70,6 @@
    #define BCR 0xdc
    #define BCR_WPD BIT(0)

    -#define SPIBASE_APL_SZ 4096
    -
    #define GPIOBASE_ICH0 0x58
    #define GPIOCTRL_ICH0 0x5C
    #define GPIOBASE_ICH6 0x48
    @@ -1126,26 +1125,19 @@ static int lpc_ich_init_spi(struct pci_dev *dev)
    break;

    case INTEL_SPI_BXT: {
    - unsigned int p2sb = PCI_DEVFN(13, 0);
    unsigned int spi = PCI_DEVFN(13, 2);
    - struct pci_bus *bus = dev->bus;
    + int ret;

    /*
    * The P2SB is hidden by BIOS and we need to unhide it in
    * order to read BAR of the SPI flash device. Once that is
    * done we hide it again.
    */
    - pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x0);
    - pci_bus_read_config_dword(bus, spi, PCI_BASE_ADDRESS_0,
    - &spi_base);
    - if (spi_base != ~0) {
    - res->start = spi_base & 0xfffffff0;
    - res->end = res->start + SPIBASE_APL_SZ - 1;
    -
    - lpc_ich_test_spi_write(dev, spi, info);
    - }
    + ret = pci_p2sb_bar(dev, spi, res);
    + if (ret)
    + return ret;

    - pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1);
    + lpc_ich_test_spi_write(dev, spi, info);
    break;
    }

    --
    2.30.1
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