Messages in this thread | | | Date | Thu, 4 Mar 2021 08:25:56 -0800 | From | Sean Christopherson <> | Subject | Re: [PATCH v3 6/9] KVM: vmx/pmu: Add MSR_ARCH_LBR_CTL emulation for Arch LBR |
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On Thu, Mar 04, 2021, Xu, Like wrote: > On 2021/3/4 1:19, Sean Christopherson wrote: > > > @@ -4463,6 +4470,8 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) > > > vmcs_writel(GUEST_SYSENTER_ESP, 0); > > > vmcs_writel(GUEST_SYSENTER_EIP, 0); > > > vmcs_write64(GUEST_IA32_DEBUGCTL, 0); > > > + if (cpu_has_vmx_arch_lbr()) > > > + vmcs_write64(GUEST_IA32_LBR_CTL, 0); > > Not that any guest is likely to care, but is the MSR cleared on INIT? The SDM > > has specific language for warm reset, but I can't find anything for INIT. > > > > On a warm reset, all LBR MSRs, including IA32_LBR_DEPTH, have their values > > preserved. However, IA32_LBR_CTL.LBREn is cleared to 0, disabling LBRs. If a > > warm reset is triggered while the processor is in C6, also known as warm init, > > all LBR MSRs will be reset to their initial values. > > I was told that the reset behavior of GUEST_IA32_LBR_CTL > would be the same as the GUEST_IA32_DEBUGCTL (true for INIT as well).
Yes, and DEBUGCTL is preserved on INIT.
if (!init_event) { vmcs_write32(GUEST_SYSENTER_CS, 0); vmcs_writel(GUEST_SYSENTER_ESP, 0); vmcs_writel(GUEST_SYSENTER_EIP, 0); vmcs_write64(GUEST_IA32_DEBUGCTL, 0); }
Table 22-10 in the SDM:
All Other MSRs | Pwr up or Reset: | INIT: Undefined Unchanged
If IA32_LBR_DEPTH is weirdly exempt, it needs to be documented. I doubt that's the case though.
> It looks we have not strictly distinguished the guest's power concept C*. > Do we have two trap paths for "warm reset" and "warm init" ?
No. Despite the name .vcpu_reset, KVM doesn't even have a RESET path, userspace is responsible for modelling RESET.
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