Messages in this thread Patch in this message | | | From | guoren@kernel ... | Subject | [PATCH v5 7/7] xtensa: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 | Date | Sun, 28 Mar 2021 06:30:28 +0000 |
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From: Guo Ren <guoren@linux.alibaba.com>
We don't have native hw xchg16 instruction, so let qspinlock generic code to deal with it.
Using the full-word atomic xchg instructions implement xchg16 has the semantic risk for atomic operations.
This patch cancels the dependency of on qspinlock generic code on architecture's xchg16.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Chris Zankel <chris@zankel.net> Cc: Max Filippov <jcmvbkbc@gmail.com> --- arch/xtensa/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 9ad6b7b82707..f19d780638f7 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -9,6 +9,7 @@ config XTENSA select ARCH_HAS_DMA_SET_UNCACHED if MMU select ARCH_USE_QUEUED_RWLOCKS select ARCH_USE_QUEUED_SPINLOCKS + select ARCH_USE_QUEUED_SPINLOCKS_XCHG32 select ARCH_WANT_FRAME_POINTERS select ARCH_WANT_IPC_PARSE_VERSION select BUILDTIME_TABLE_SORT -- 2.17.1
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