Messages in this thread | | | Date | Wed, 24 Mar 2021 13:32:40 +0100 | From | Andrew Lunn <> | Subject | Re: [PATCH] net: phy: dp83867: perform soft reset and retain established link |
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On Tue, Mar 23, 2021 at 08:00:06PM -0500, praneeth@ti.com wrote: > From: Praneeth Bajjuri <praneeth@ti.com> > > Current logic is performing hard reset and causing the programmed > registers to be wiped out. > > as per datasheet: https://www.ti.com/lit/ds/symlink/dp83867cr.pdf > 8.6.26 Control Register (CTRL) > do SW_RESTART to perform a reset not including the registers and is > acceptable to do this if a link is already present.
I don't see any code here to determine if the like is present. What if the cable is not plugged in?
> @@ -826,7 +826,7 @@ static int dp83867_phy_reset(struct phy_device *phydev) > { > int err; > > - err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET); > + err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART); > if (err < 0) > return err;
The code continues
usleep_range(10, 20);
/* After reset FORCE_LINK_GOOD bit is set. Although the * default value should be unset. Disable FORCE_LINK_GOOD * for the phy to work properly. */ return phy_modify(phydev, MII_DP83867_PHYCTRL, DP83867_PHYCR_FORCE_LINK_GOOD, 0); }
Do you still need to clear the FORCE_LINK_GOOD bit after a restart?
Andrew
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