Messages in this thread | | | Subject | Re: [PATCH] drm: xlnx: call pm_runtime_get_sync before setting pixel clock | From | "quanyang.wang" <> | Date | Tue, 16 Mar 2021 19:46:45 +0800 |
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Ping.
Any comment on this patch?
Thanks,
Quanyang
On 3/10/21 12:59 PM, quanyang.wang@windriver.com wrote: > From: Quanyang Wang <quanyang.wang@windriver.com> > > The Runtime PM subsystem will force the device "fd4a0000.zynqmp-display" > to enter suspend state while booting if the following conditions are met: > - the usage counter is zero (pm_runtime_get_sync hasn't been called yet) > - no 'active' children (no zynqmp-dp-snd-xx node under dpsub node) > - no other device in the same power domain (dpdma node has no > "power-domains = <&zynqmp_firmware PD_DP>" property) > > So there is a scenario as below: > 1) DP device enters suspend state <- call zynqmp_gpd_power_off > 2) zynqmp_disp_crtc_setup_clock <- configurate register VPLL_FRAC_CFG > 3) pm_runtime_get_sync <- call zynqmp_gpd_power_on and clear previous > VPLL_FRAC_CFG configuration > 4) clk_prepare_enable(disp->pclk) <- enable failed since VPLL_FRAC_CFG > configuration is corrupted > > From above, we can see that pm_runtime_get_sync may clear register > VPLL_FRAC_CFG configuration and result the failure of clk enabling. > Putting pm_runtime_get_sync at the very beginning of the function > zynqmp_disp_crtc_atomic_enable can resolve this issue. > > Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com> > --- > drivers/gpu/drm/xlnx/zynqmp_disp.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c > index 148add0ca1d6..909e6c265406 100644 > --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c > +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c > @@ -1445,9 +1445,10 @@ zynqmp_disp_crtc_atomic_enable(struct drm_crtc *crtc, > struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; > int ret, vrefresh; > > + pm_runtime_get_sync(disp->dev); > + > zynqmp_disp_crtc_setup_clock(crtc, adjusted_mode); > > - pm_runtime_get_sync(disp->dev); > ret = clk_prepare_enable(disp->pclk); > if (ret) { > dev_err(disp->dev, "failed to enable a pixel clock\n");
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