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    Subject[PATCH 5.11 617/775] drm/amdgpu: fix CGTS_TCC_DISABLE register offset on gfx10.3
    Date
    From: Marek Olšák <marek.olsak@amd.com>

    commit 4112c00354004cbb1bf56f0114fa9951bf6b13ed upstream.

    This fixes incorrect TCC harvesting info reported to userspace.
    The impact was a very very tiny performance degradation (unnecessary
    GL2 cache flushes).

    Signed-off-by: Marek Olšák <marek.olsak@amd.com>
    Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Cc: stable@vger.kernel.org
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 22 ++++++++++------------
    1 file changed, 10 insertions(+), 12 deletions(-)

    --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
    +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
    @@ -71,6 +71,11 @@
    #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8
    #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L

    +#define mmCGTS_TCC_DISABLE_gc_10_3 0x5006
    +#define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1
    +#define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007
    +#define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1
    +
    #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55
    #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0
    #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0
    @@ -99,10 +104,6 @@
    #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580
    #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0

    -#define mmCGTS_TCC_DISABLE_Vangogh 0x5006
    -#define mmCGTS_TCC_DISABLE_Vangogh_BASE_IDX 1
    -#define mmCGTS_USER_TCC_DISABLE_Vangogh 0x5007
    -#define mmCGTS_USER_TCC_DISABLE_Vangogh_BASE_IDX 1
    #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025
    #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1
    #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026
    @@ -4942,15 +4943,12 @@ static void gfx_v10_0_get_tcc_info(struc
    /* TCCs are global (not instanced). */
    uint32_t tcc_disable;

    - switch (adev->asic_type) {
    - case CHIP_VANGOGH:
    - tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_Vangogh) |
    - RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_Vangogh);
    - break;
    - default:
    + if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
    + tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
    + RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
    + } else {
    tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
    - RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
    - break;
    + RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
    }

    adev->gfx.config.tcc_disabled_mask =

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