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    Subject[PATCH 5.11 644/775] drm/i915/gt: Correct surface base address for renderclear
    Date
    From: Chris Wilson <chris@chris-wilson.co.uk>

    commit 81ce8f04aa96f7f6cae05770f68b5d15be91f5a2 upstream.

    The surface_state_base is an offset into the batch, so we need to pass
    the correct batch address for STATE_BASE_ADDRESS.

    Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
    Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
    Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
    Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
    Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
    Cc: Hans de Goede <hdegoede@redhat.com>
    Cc: Hans de Goede <hdegoede@redhat.com>
    Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
    Cc: <stable@vger.kernel.org> # v5.7+
    Link: https://patchwork.freedesktop.org/patch/msgid/20210210122728.20097-1-chris@chris-wilson.co.uk
    (cherry picked from commit 1914911f4aa08ddc05bae71d3516419463e0c567)
    Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/gpu/drm/i915/gt/gen7_renderclear.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
    +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
    @@ -240,7 +240,7 @@ gen7_emit_state_base_address(struct batc
    /* general */
    *cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY;
    /* surface */
    - *cs++ = batch_addr(batch) | surface_state_base | BASE_ADDRESS_MODIFY;
    + *cs++ = (batch_addr(batch) + surface_state_base) | BASE_ADDRESS_MODIFY;
    /* dynamic */
    *cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY;
    /* indirect */

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